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author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:13 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:13 -0400 |
commit | 1c8dfd92543aba5f49e464b17e7e8143fc01a58c (patch) | |
tree | 3c5b9059b07e8d0bccdf826249330bfcb8c5c1cc /src/cpu/inorder/resources | |
parent | 63db33c4b1cd7a071c2a2fe47bda21a73618d054 (diff) | |
download | gem5-1c8dfd92543aba5f49e464b17e7e8143fc01a58c.tar.xz |
inorder-alpha-port: initial inorder support of ALPHA
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
Diffstat (limited to 'src/cpu/inorder/resources')
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 2 | ||||
-rw-r--r-- | src/cpu/inorder/resources/mult_div_unit.cc | 2 | ||||
-rw-r--r-- | src/cpu/inorder/resources/tlb_unit.cc | 25 | ||||
-rw-r--r-- | src/cpu/inorder/resources/tlb_unit.hh | 5 |
4 files changed, 27 insertions, 7 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 772437638..d273d7247 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -32,7 +32,7 @@ #include <vector> #include <list> #include "arch/isa_traits.hh" -#include "arch/mips/locked_mem.hh" +#include "arch/locked_mem.hh" #include "arch/utility.hh" #include "cpu/inorder/resources/cache_unit.hh" #include "cpu/inorder/pipeline_traits.hh" diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc index b31d60ad5..df9d4c293 100644 --- a/src/cpu/inorder/resources/mult_div_unit.cc +++ b/src/cpu/inorder/resources/mult_div_unit.cc @@ -47,7 +47,7 @@ MultDivUnit::MultDivUnit(string res_name, int res_id, int res_width, div16RepeatRate(params->div16RepeatRate), div16Latency(params->div16Latency), div24RepeatRate(params->div24RepeatRate), div24Latency(params->div24Latency), div32RepeatRate(params->div32RepeatRate), div32Latency(params->div32Latency), - lastMDUCycle(0) + lastMDUCycle(0), lastOpType(No_OpClass) { } void diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc index b3757d707..fbc6bc195 100644 --- a/src/cpu/inorder/resources/tlb_unit.cc +++ b/src/cpu/inorder/resources/tlb_unit.cc @@ -33,6 +33,7 @@ #include <list> #include "arch/isa_traits.hh" #include "cpu/inorder/pipeline_traits.hh" +#include "cpu/inorder/first_stage.hh" #include "cpu/inorder/resources/tlb_unit.hh" #include "cpu/inorder/cpu.hh" @@ -44,11 +45,26 @@ TLBUnit::TLBUnit(string res_name, int res_id, int res_width, int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params) : InstBuffer(res_name, res_id, res_width, res_latency, _cpu, params) { + // Hard-Code Selection For Now + if (res_name == "I-TLB") + _tlb = params->itb; + else if (res_name == "D-TLB") + _tlb = params->dtb; + else + fatal("Unrecognized TLB name passed by user"); + for (int i=0; i < MaxThreads; i++) { tlbBlocked[i] = false; } } +TheISA::TLB* +TLBUnit::tlb() +{ + return _tlb; + +} + void TLBUnit::init() { @@ -82,7 +98,7 @@ TLBUnit::execute(int slot_idx) // After this is working, change this to a reinterpret cast // for performance considerations TLBUnitRequest* tlb_req = dynamic_cast<TLBUnitRequest*>(reqMap[slot_idx]); - assert(tlb_req); + assert(tlb_req != 0x0); DynInstPtr inst = tlb_req->inst; int tid, seq_num, stage_num; @@ -93,12 +109,15 @@ TLBUnit::execute(int slot_idx) tlb_req->fault = NoFault; + assert(cpu->thread[tid]->getTC() != 0x0); + assert(cpu->pipelineStage[stage_num] != 0x0); + switch (tlb_req->cmd) { case FetchLookup: { tlb_req->fault = - this->cpu->itb->translateAtomic(tlb_req->memReq, + _tlb->translateAtomic(tlb_req->memReq, cpu->thread[tid]->getTC(), false, true); if (tlb_req->fault != NoFault) { @@ -129,7 +148,7 @@ TLBUnit::execute(int slot_idx) tid, seq_num, tlb_req->memReq->getVaddr()); tlb_req->fault = - this->cpu->itb->translateAtomic(tlb_req->memReq, + _tlb->translateAtomic(tlb_req->memReq, cpu->thread[tid]->getTC()); if (tlb_req->fault != NoFault) { diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh index c7fee6030..b53f251fc 100644 --- a/src/cpu/inorder/resources/tlb_unit.hh +++ b/src/cpu/inorder/resources/tlb_unit.hh @@ -67,14 +67,15 @@ class TLBUnit : public InstBuffer { bool tlbBlocked[ThePipeline::MaxThreads]; + TheISA::TLB* tlb(); + protected: /** List of instructions this resource is currently * processing. */ std::list<DynInstPtr> instList; - /** @todo: Add Resource Stats Here */ - + TheISA::TLB *_tlb; }; class TLBUnitEvent : public ResourceEvent { |