inorder-fetch: update model to use predecoder

2 files changed, 36 insertions, 42 deletions

diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 68daee512..3b4dd0420 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -34,6 +34,7 @@
 #include "arch/isa_traits.hh"
 #include "arch/locked_mem.hh"
 #include "arch/utility.hh"
+#include "arch/predecoder.hh"
 #include "cpu/inorder/resources/cache_unit.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/cpu.hh"
@@ -81,7 +82,8 @@ CacheUnit::CachePort::recvRetry()
 CacheUnit::CacheUnit(string res_name, int res_id, int res_width,
         int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
     : Resource(res_name, res_id, res_width, res_latency, _cpu),
-      retryPkt(NULL), retrySlot(-1), cacheBlocked(false)
+      retryPkt(NULL), retrySlot(-1), cacheBlocked(false),
+      predecoder(NULL)
 {
     cachePort = new CachePort(this);
 }
@@ -259,35 +261,11 @@ CacheUnit::execute(int slot_num)
                     "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
                     tid, inst->seqNum);
 
-            MachInst mach_inst = cache_req->dataPkt->get<MachInst>();
 
-            /**
-             * @TODO: May Need This Function for Endianness-Compatibility
-             *  mach_inst =
-             *    gtoh(*reinterpret_cast<MachInst *>(&cacheData[tid][offset]));
-             */
-
-            DPRINTF(InOrderCachePort,
-                    "[tid:%i]: Fetched instruction is %08p\n",
-                    tid, mach_inst);
-
-            // ExtMachInst ext_inst = makeExtMI(mach_inst, cpu->tcBase(tid));
-
-            inst->setMachInst(mach_inst);
-            inst->setASID(tid);
-            inst->setThreadState(cpu->thread[tid]);
-
-            DPRINTF(InOrderStage, "[tid:%i]: Instruction [sn:%i] is: %s\n",
+            DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
                     tid, seq_num, inst->staticInst->disassemble(inst->PC));
 
-            // Set Up More TraceData info
-            if (inst->traceData) {
-                inst->traceData->setStaticInst(inst->staticInst);
-                inst->traceData->setPC(inst->readPC());
-            }
-
             delete cache_req->dataPkt;
-
             cache_req->done();
         } else {
             DPRINTF(InOrderCachePort,
@@ -396,7 +374,6 @@ CacheUnit::doDataAccess(DynInstPtr inst)
         cache_req->dataPkt->dataStatic(cache_req->reqData);
     } else if (cache_req->dataPkt->isWrite()) {
         cache_req->dataPkt->dataStatic(&cache_req->inst->storeData);
-
     }
 
     cache_req->dataPkt->time = curTick;
@@ -514,6 +491,33 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
             DPRINTF(InOrderCachePort,
                     "[tid:%u]: [sn:%i]: Processing fetch access\n",
                     tid, inst->seqNum);
+
+            // NOTE: This is only allowing a thread to fetch one line
+            //       at a time. Re-examine when/if prefetching
+            //       gets implemented.
+            //memcpy(fetchData[tid], cache_pkt->getPtr<uint8_t>(),
+            //     cache_pkt->getSize());
+
+            // Get the instruction from the array of the cache line.
+            // @todo: update thsi
+            ExtMachInst ext_inst;
+            StaticInstPtr staticInst = NULL;
+            Addr inst_pc = inst->readPC();
+            MachInst mach_inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
+                                (cache_pkt->getPtr<uint8_t>()));
+
+            predecoder.setTC(cpu->thread[tid]->getTC());
+            predecoder.moreBytes(inst_pc, inst_pc, mach_inst);
+            ext_inst = predecoder.getExtMachInst();
+
+            inst->setMachInst(ext_inst);
+
+            // Set Up More TraceData info
+            if (inst->traceData) {
+                inst->traceData->setStaticInst(inst->staticInst);
+                inst->traceData->setPC(inst->readPC());
+            }
+
         } else if (inst->staticInst && inst->isMemRef()) {
             DPRINTF(InOrderCachePort,
                     "[tid:%u]: [sn:%i]: Processing cache access\n",
@@ -546,7 +550,6 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
                         "[tid:%u]: [sn:%i]: Data stored was: %08p\n",
                         tid, inst->seqNum,
                         getMemData(cache_pkt));
-
             }
 
             delete cache_pkt;
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 4cde686b8..06ccf3bec 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -36,8 +36,7 @@
 #include <list>
 #include <string>
 
-//#include "cpu/inorder/params.hh"
-
+#include "arch/predecoder.hh"
 #include "cpu/inorder/resource.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "mem/packet.hh"
@@ -154,19 +153,12 @@ class CacheUnit : public Resource
     /** Align a PC to the start of an I-cache block. */
     Addr cacheBlockAlignPC(Addr addr)
     {
-        //addr = TheISA::realPCToFetchPC(addr);
         return (addr & ~(cacheBlkMask));
     }
 
     /** Returns a specific port. */
     Port *getPort(const std::string &if_name, int idx);
 
-    /** Fetch on behalf of an instruction. Will check to see
-     *  if instruction is actually in resource before
-     *  trying to fetch.
-     */
-    //Fault doFetchAccess(DynInstPtr inst);
-
     /** Read/Write on behalf of an instruction.
      *  curResSlot needs to be a valid value in instruction.
      */
@@ -207,17 +199,16 @@ class CacheUnit : public Resource
         return (addr & ~(cacheBlkMask));
     }
 
-    /** THINGS USED FOR FETCH */
-    // NO LONGER USED BY COMMENT OUT UNTIL FULL VERIFICATION
     /** The mem line being fetched. */
-    //uint8_t *cacheData[ThePipeline::MaxThreads];
+    uint8_t *fetchData[ThePipeline::MaxThreads];
 
+    /** @TODO: Move functionaly of fetching more than
+        one instruction to 'fetch unit'*/
     /** The Addr of the cacheline that has been loaded. */
     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
-
     //unsigned fetchOffset[ThePipeline::MaxThreads];
 
-    /** @todo: Add Resource Stats Here */
+    TheISA::Predecoder predecoder;
 };
 
 struct CacheSchedEntry : public ThePipeline::ScheduleEntry