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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:37 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:37 -0400 |
| commit | 71018f5e8b59c359065580a41a96f1a78a88dea9 (patch) | |
| tree | 17486a65f463cb7bb9085182edc2d480cde7b1f6 /src/cpu/inorder/resources | |
| parent | 34b2500f09639e950cb590a34e51a1db853abf11 (diff) | |
| download | gem5-71018f5e8b59c359065580a41a96f1a78a88dea9.tar.xz | |
inorder: remove stalls on trap squash
Diffstat (limited to 'src/cpu/inorder/resources')
| -rw-r--r-- | src/cpu/inorder/resources/fetch_seq_unit.cc | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc index 5d90f71d3..072ecb76f 100644 --- a/src/cpu/inorder/resources/fetch_seq_unit.cc +++ b/src/cpu/inorder/resources/fetch_seq_unit.cc @@ -116,6 +116,9 @@ FetchSeqUnit::execute(int slot_num) // If it's a return, then we must wait for resolved address. // The Predictor will mark a return a false as "not taken" // if there is no RAS entry + DPRINTF(InOrderFetchSeq, "[tid:%d]: Setting block signal " + "for stage %i.\n", + tid, stage_num); cpu->pipelineStage[stage_num]-> toPrevStages->stageBlock[stage_num][tid] = true; pcValid[tid] = false; @@ -215,8 +218,16 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage, // Unblock Any Stages Waiting for this information to be updated ... if (!pcValid[tid]) { + DPRINTF(InOrderFetchSeq, "[tid:%d]: Setting unblock signal " + "for stage %i.\n", + tid, pcBlockStage[tid]); + + // Need to use "fromNextStages" instead of "toPrevStages" + // because the timebuffer will have already have advanced + // in the tick function and this squash function will happen after + // the tick cpu->pipelineStage[pcBlockStage[tid]]-> - toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true; + fromNextStages->stageUnblock[pcBlockStage[tid]][tid] = true; } pcValid[tid] = true; @@ -291,6 +302,8 @@ FetchSeqUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst) "%s.\n", tid, pc[tid]); DPRINTF(InOrderFetchSeq, "[tid:%i]: Trap updating to PC: " "%s.\n", tid, pc[tid]); + + cpu->removePipelineStalls(tid); } void |