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author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:38 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:38 -0400 |
commit | e8082a28c8ee36d6e7e1982952fc545224eb33e7 (patch) | |
tree | 0ddce2a133a2bd82a10944d6f3918e4d36d7d28d /src/cpu/inorder/resources | |
parent | 379c23199e957083dd1656c0686ee258facc6e19 (diff) | |
download | gem5-e8082a28c8ee36d6e7e1982952fc545224eb33e7.tar.xz |
inorder: don't stall after stores
once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed
Diffstat (limited to 'src/cpu/inorder/resources')
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 10 | ||||
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.hh | 4 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 83eb617aa..c627466a1 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -240,17 +240,17 @@ CacheUnit::removeAddrDependency(DynInstPtr inst) inst->unsetMemAddr(); // Erase from Address List - vector<Addr>::iterator vect_it = find(addrList[tid].begin(), + std::list<Addr>::iterator list_it = find(addrList[tid].begin(), addrList[tid].end(), mem_addr); - assert(vect_it != addrList[tid].end() || inst->splitInst); + assert(list_it != addrList[tid].end() || inst->splitInst); - if (vect_it != addrList[tid].end()) { + if (list_it != addrList[tid].end()) { DPRINTF(AddrDep, "[tid:%i]: [sn:%i] Address %08p removed from dependency " - "list\n", inst->readTid(), inst->seqNum, (*vect_it)); + "list\n", inst->readTid(), inst->seqNum, (*list_it)); - addrList[tid].erase(vect_it); + addrList[tid].erase(list_it); // Erase From Address Map (Used for Debugging) addrMap[tid].erase(addrMap[tid].find(mem_addr)); diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index 7daf5f4a0..dd6fa7638 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -187,9 +187,9 @@ class CacheUnit : public Resource bool cachePortBlocked; - std::vector<Addr> addrList[ThePipeline::MaxThreads]; + std::list<Addr> addrList[ThePipeline::MaxThreads]; - std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads]; + m5::hash_map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads]; public: int cacheBlkSize; |