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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
| commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
| tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/cpu/inorder/resources | |
| parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
| download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz | |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/cpu/inorder/resources')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 3 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/fetch_unit.cc | 3 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/tlb_unit.hh | 8 |
3 files changed, 11 insertions, 3 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 0ab9f0579..33bd9e619 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -367,6 +367,7 @@ CacheUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req, if (cache_req->memReq == NULL) { cache_req->memReq = new Request(cpu->asid[tid], aligned_addr, acc_size, flags, + cpu->dataMasterId(), inst->instAddr(), cpu->readCpuId(), //@todo: use context id tid); @@ -379,6 +380,7 @@ CacheUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req, inst->split2ndAddr, acc_size, flags, + cpu->dataMasterId(), inst->instAddr(), cpu->readCpuId(), tid); @@ -1070,6 +1072,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt) inst->getMemAddr(), inst->totalSize, 0, + cpu->dataMasterId(), 0); split_pkt = new Packet(cache_req->memReq, cache_req->pktCmd, diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc index b32134e00..cc4b8b53e 100644 --- a/src/cpu/inorder/resources/fetch_unit.cc +++ b/src/cpu/inorder/resources/fetch_unit.cc @@ -159,7 +159,8 @@ FetchUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req, if (cache_req->memReq == NULL) { cache_req->memReq = new Request(tid, aligned_addr, acc_size, flags, - inst->instAddr(), cpu->readCpuId(), tid); + cpu->instMasterId(), inst->instAddr(), cpu->readCpuId(), + tid); DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n", inst->seqNum, &cache_req->memReq, cache_req->memReq); } diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh index caccb5a9f..6846bdc87 100644 --- a/src/cpu/inorder/resources/tlb_unit.hh +++ b/src/cpu/inorder/resources/tlb_unit.hh @@ -118,7 +118,9 @@ class TLBUnitRequest : public ResourceRequest { req_size = sizeof(TheISA::MachInst); flags = 0; inst->fetchMemReq = new Request(inst->readTid(), aligned_addr, - req_size, flags, inst->instAddr(), + req_size, flags, + res->cpu->instMasterId(), + inst->instAddr(), res->cpu->readCpuId(), inst->readTid()); memReq = inst->fetchMemReq; @@ -132,7 +134,9 @@ class TLBUnitRequest : public ResourceRequest { } inst->dataMemReq = new Request(inst->readTid(), aligned_addr, - req_size, flags, inst->instAddr(), + req_size, flags, + res->cpu->dataMasterId(), + inst->instAddr(), res->cpu->readCpuId(), inst->readTid()); memReq = inst->dataMemReq; |