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| author | Korey Sewell <ksewell@umich.edu> | 2009-02-20 11:02:48 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-02-20 11:02:48 -0500 |
| commit | 6c5afe6346b31edf6af245002c270a3c26618833 (patch) | |
| tree | feae2798bdaab7838e506f4f10138a4669f21828 /src/cpu/inorder/thread_context.hh | |
| parent | c41c9cf3a68bbda47b2304daeb145555dd63e5d3 (diff) | |
| download | gem5-6c5afe6346b31edf6af245002c270a3c26618833.tar.xz | |
Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context
Diffstat (limited to 'src/cpu/inorder/thread_context.hh')
| -rw-r--r-- | src/cpu/inorder/thread_context.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index 919d5d2b6..708dcf6b3 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -147,7 +147,7 @@ class InOrderThreadContext : public ThreadContext virtual TheISA::MachInst getInst(); /** Copies the architectural registers from another TC into this TC. */ - virtual void copyArchRegs(ThreadContext *tc); + virtual void copyArchRegs(ThreadContext *src_tc); /** Resets all architectural registers to 0. */ virtual void clearArchRegs(); |