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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
commit | 25884a87733cd35ef6613aaef9a8a08194267552 (patch) | |
tree | 3eb831102c76206ba5ba4e19b94810be67ce108f /src/cpu/inorder/thread_context.hh | |
parent | 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 (diff) | |
download | gem5-25884a87733cd35ef6613aaef9a8a08194267552.tar.xz |
Registers: Get rid of the float register width parameter.
Diffstat (limited to 'src/cpu/inorder/thread_context.hh')
-rw-r--r-- | src/cpu/inorder/thread_context.hh | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index aac8901b3..327f8ac71 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -152,12 +152,8 @@ class InOrderThreadContext : public ThreadContext /** Reads an integer register. */ virtual uint64_t readIntReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx, int width); - virtual FloatReg readFloatReg(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx, int width); - virtual FloatRegBits readFloatRegBits(int reg_idx); virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid); @@ -165,12 +161,8 @@ class InOrderThreadContext : public ThreadContext /** Sets an integer register to a value. */ virtual void setIntReg(int reg_idx, uint64_t val); - virtual void setFloatReg(int reg_idx, FloatReg val, int width); - virtual void setFloatReg(int reg_idx, FloatReg val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val); virtual void setRegOtherThread(int misc_reg, const MiscReg &val, |