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| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:42 -0400 |
| commit | 08c1835bef5caa72dc931ed529e4ed3470989d4f (patch) | |
| tree | c7523438790ccf9d6206fe328291bec468d84b48 /src/cpu/inorder | |
| parent | 670fc52f1812727457eaf6cb4fca1a520a6a8c20 (diff) | |
| download | gem5-08c1835bef5caa72dc931ed529e4ed3470989d4f.tar.xz | |
cpu: Remove CpuPort and use MasterPort in the CPU classes
This patch changes the port in the CPU classes to use MasterPort
instead of the derived CpuPort. The functions of the CpuPort are now
distributed across the relevant subclasses. The port accessor
functions (getInstPort and getDataPort) now return a MasterPort
instead of a CpuPort. This simplifies creating derivative CPUs that do
not use the CpuPort.
Diffstat (limited to 'src/cpu/inorder')
| -rw-r--r-- | src/cpu/inorder/cpu.cc | 2 | ||||
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 1ba8e55b6..5c07621e3 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -84,7 +84,7 @@ using namespace ThePipeline; InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit, const std::string& name) : - CpuPort(_cacheUnit->name() + name, _cacheUnit->cpu), + MasterPort(_cacheUnit->name() + name, _cacheUnit->cpu), cacheUnit(_cacheUnit) { } diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 7ca4355de..e69c9d47b 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 ARM Limited + * Copyright (c) 2012-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -112,10 +112,10 @@ class InOrderCPU : public BaseCPU void verifyMemoryMode() const; /** Return a reference to the data port. */ - virtual CpuPort &getDataPort() { return dataPort; } + virtual MasterPort &getDataPort() { return dataPort; } /** Return a reference to the instruction port. */ - virtual CpuPort &getInstPort() { return instPort; } + virtual MasterPort &getInstPort() { return instPort; } /** CPU ID */ int cpu_id; @@ -158,7 +158,7 @@ class InOrderCPU : public BaseCPU * CachePort class for the in-order CPU, interacting with a * specific CacheUnit in the pipeline. */ - class CachePort : public CpuPort + class CachePort : public MasterPort { private: |