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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
| commit | b3f930c884ef23e4d784553fdccc91a772334fd7 (patch) | |
| tree | cafe3076cb93173cb0587e7f6c718efa178463e6 /src/cpu/inorder | |
| parent | f85286b3debf4a4a94d3b959e5bb880be81bd692 (diff) | |
| download | gem5-b3f930c884ef23e4d784553fdccc91a772334fd7.tar.xz | |
CPU: Moving towards a more general port across CPU models
This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.
Diffstat (limited to 'src/cpu/inorder')
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 4766a1ac1..40af48b19 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -44,9 +44,6 @@ class InOrderCPU(BaseCPU): fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get instructions from") dataMemPort = Param.String("dcache_port" , "Name of Memory Port to get data from") - icache_port = Port("Instruction Port") - dcache_port = Port("Data Port") - _cached_ports = ['icache_port', 'dcache_port'] fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)") memBlockSize = Param.Unsigned(64, "Memory Block Size") |