ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.

This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.

On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.

On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.

7 files changed, 0 insertions, 108 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 6cd938dc6..5f723d0b3 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1445,21 +1445,6 @@ InOrderCPU::syscall(int64_t callnum, ThreadID tid)
 }
 #endif
 
-void
-InOrderCPU::prefetch(DynInstPtr inst)
-{
-    Resource *mem_res = resPool->getResource(dataPortIdx);
-    return mem_res->prefetch(inst);
-}
-
-void
-InOrderCPU::writeHint(DynInstPtr inst)
-{
-    Resource *mem_res = resPool->getResource(dataPortIdx);
-    return mem_res->writeHint(inst);
-}
-
-
 TheISA::TLB*
 InOrderCPU::getITBPtr()
 {
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index df6617d56..65c822331 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -530,16 +530,6 @@ class InOrderCPU : public BaseCPU
     Fault write(DynInstPtr inst, uint8_t *data, unsigned size,
                 Addr addr, unsigned flags, uint64_t *write_res = NULL);
 
-    /** Forwards an instruction prefetch to the appropriate data
-     *  resource (indexes into Resource Pool thru "dataPortIdx")
-     */
-    void prefetch(DynInstPtr inst);
-
-    /** Forwards an instruction writeHint to the appropriate data
-     *  resource (indexes into Resource Pool thru "dataPortIdx")
-     */
-    void writeHint(DynInstPtr inst);
-
     /** Executes a syscall.*/
     void syscall(int64_t callnum, ThreadID tid);
 
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index f672082f3..d848226c4 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -346,38 +346,6 @@ InOrderDynInst::syscall(int64_t callnum)
 #endif
 
 void
-InOrderDynInst::prefetch(Addr addr, unsigned flags)
-{
-    cpu->prefetch(this);
-}
-
-void
-InOrderDynInst::writeHint(Addr addr, int size, unsigned flags)
-{
-    cpu->writeHint(this);
-}
-
-/**
- * @todo Need to find a way to get the cache block size here.
- */
-Fault
-InOrderDynInst::copySrcTranslate(Addr src)
-{
-    // Not currently supported.
-    return NoFault;
-}
-
-/**
- * @todo Need to find a way to get the cache block size here.
- */
-Fault
-InOrderDynInst::copy(Addr dest)
-{
-    // Not currently supported.
-    return NoFault;
-}
-
-void
 InOrderDynInst::releaseReq(ResourceRequest* req)
 {
     std::list<ResourceRequest*>::iterator list_it = reqList.begin();
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 105e37657..a67fe46c2 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -506,10 +506,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     /** Calls a syscall. */
     void syscall(int64_t callnum);
 #endif
-    void prefetch(Addr addr, unsigned flags);
-    void writeHint(Addr addr, int size, unsigned flags);
-    Fault copySrcTranslate(Addr src);
-    Fault copy(Addr dest);
 
     ////////////////////////////////////////////////////////////
     //
diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index f0c3354b2..06ef95e44 100644
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -154,12 +154,6 @@ class Resource {
     virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
     { panic("doCacheAccess undefined for %s", name()); return NoFault; }
 
-    virtual void prefetch(DynInstPtr inst)
-    { panic("prefetch undefined for %s", name()); }
-
-    virtual void writeHint(DynInstPtr inst)
-    { panic("writeHint undefined for %s", name()); }
-
     /** Squash All Requests After This Seq Num */
     virtual void squash(DynInstPtr inst, int stage_num,
                         InstSeqNum squash_seq_num, ThreadID tid);
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index e7f689ffa..5f9ddd372 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -842,43 +842,6 @@ CacheUnit::execute(int slot_num)
     }
 }
 
-void
-CacheUnit::prefetch(DynInstPtr inst)
-{
-    warn_once("Prefetching currently unimplemented");
-
-    CacheReqPtr cache_req
-        = dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
-    assert(cache_req);
-
-    // Clean-Up cache resource request so
-    // other memory insts. can use them
-    cache_req->setCompleted();
-    cachePortBlocked = false;
-    cache_req->setMemAccPending(false);
-    cache_req->setMemAccCompleted();
-    inst->unsetMemAddr();
-}
-
-
-void
-CacheUnit::writeHint(DynInstPtr inst)
-{
-    warn_once("Write Hints currently unimplemented");
-
-    CacheReqPtr cache_req
-        = dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
-    assert(cache_req);
-
-    // Clean-Up cache resource request so
-    // other memory insts. can use them
-    cache_req->setCompleted();
-    cachePortBlocked = false;
-    cache_req->setMemAccPending(false);
-    cache_req->setMemAccCompleted();
-    inst->unsetMemAddr();
-}
-
 // @TODO: Split into doCacheRead() and doCacheWrite()
 Fault
 CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res,
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 2f369db7c..49b394c61 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -176,10 +176,6 @@ class CacheUnit : public Resource
     Fault doCacheAccess(DynInstPtr inst, uint64_t *write_result=NULL,
                         CacheReqPtr split_req=NULL);
 
-    void prefetch(DynInstPtr inst);
-
-    void writeHint(DynInstPtr inst);
-
     uint64_t getMemData(Packet *packet);
 
     void setAddrDependency(DynInstPtr inst);