arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.

4 files changed, 19 insertions, 17 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 5815775f9..1ca0657ad 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -230,6 +230,7 @@ InOrderCPU::InOrderCPU(Params *params)
       tickEvent(this),
       stageWidth(params->stageWidth),
       resPool(new ResourcePool(this, params)),
+      isa(numThreads, NULL),
       timeBuffer(2 , 2),
       dataPort(resPool->getDataUnit(), ".dcache_port"),
       instPort(resPool->getInstUnit(), ".icache_port"),
@@ -280,6 +281,7 @@ InOrderCPU::InOrderCPU(Params *params)
     }
 
     for (ThreadID tid = 0; tid < numThreads; ++tid) {
+        isa[tid] = params->isa[tid];
         pc[tid].set(0);
         lastCommittedPC[tid].set(0);
 
@@ -358,7 +360,7 @@ InOrderCPU::InOrderCPU(Params *params)
 
         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
-        isa[tid].clear();
+        isa[tid]->clear();
 
         // Define dummy instructions and resource requests to be used.
         dummyInst[tid] = new InOrderDynInst(this, 
@@ -1249,11 +1251,11 @@ InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
 {
     if (reg_idx < FP_Base_DepTag) {
         reg_type = IntType;
-        return isa[tid].flattenIntIndex(reg_idx);
+        return isa[tid]->flattenIntIndex(reg_idx);
     } else if (reg_idx < Ctrl_Base_DepTag) {
         reg_type = FloatType;
         reg_idx -= FP_Base_DepTag;
-        return isa[tid].flattenFloatIndex(reg_idx);
+        return isa[tid]->flattenFloatIndex(reg_idx);
     } else {
         reg_type = MiscType;
         return reg_idx - TheISA::Ctrl_Base_DepTag;
@@ -1369,25 +1371,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
 MiscReg
 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    return isa[tid].readMiscRegNoEffect(misc_reg);
+    return isa[tid]->readMiscRegNoEffect(misc_reg);
 }
 
 MiscReg
 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
 {
-    return isa[tid].readMiscReg(misc_reg, tcBase(tid));
+    return isa[tid]->readMiscReg(misc_reg, tcBase(tid));
 }
 
 void
 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    isa[tid].setMiscRegNoEffect(misc_reg, val);
+    isa[tid]->setMiscRegNoEffect(misc_reg, val);
 }
 
 void
 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
+    isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
 }
 
 
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index a0fe834e8..acdac11d9 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -325,7 +325,7 @@ class InOrderCPU : public BaseCPU
     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 
     /** ISA state */
-    TheISA::ISA isa[ThePipeline::MaxThreads];
+    std::vector<TheISA::ISA *> isa;
 
     /** Dependency Tracker for Integer & Floating Point Regs */
     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index b8662ef4c..6b3375a52 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -173,7 +173,7 @@ InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
 void
 InOrderThreadContext::clearArchRegs()
 {
-    cpu->isa[thread->threadId()].clear();
+    cpu->isa[thread->threadId()]->clear();
 }
 
 
@@ -181,7 +181,7 @@ uint64_t
 InOrderThreadContext::readIntReg(int reg_idx)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenIntIndex(reg_idx);
     return cpu->readIntReg(reg_idx, tid);
 }
 
@@ -189,7 +189,7 @@ FloatReg
 InOrderThreadContext::readFloatReg(int reg_idx)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
     return cpu->readFloatReg(reg_idx, tid);
 }
 
@@ -197,7 +197,7 @@ FloatRegBits
 InOrderThreadContext::readFloatRegBits(int reg_idx)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
     return cpu->readFloatRegBits(reg_idx, tid);
 }
 
@@ -211,7 +211,7 @@ void
 InOrderThreadContext::setIntReg(int reg_idx, uint64_t val)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenIntIndex(reg_idx);
     cpu->setIntReg(reg_idx, val, tid);
 }
 
@@ -219,7 +219,7 @@ void
 InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
     cpu->setFloatReg(reg_idx, val, tid);
 }
 
@@ -227,7 +227,7 @@ void
 InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
     cpu->setFloatRegBits(reg_idx, val, tid);
 }
 
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 2dd55582e..a959d71d6 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -254,10 +254,10 @@ class InOrderThreadContext : public ThreadContext
     void setMiscReg(int misc_reg, const MiscReg &val);
 
     int flattenIntIndex(int reg)
-    { return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
+    { return cpu->isa[thread->threadId()]->flattenIntIndex(reg); }
 
     int flattenFloatIndex(int reg)
-    { return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
+    { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); }
 
     void activateContext(Cycles delay)
     { cpu->activateContext(thread->threadId(), delay); }