cpu: clean up architectural register classification

Move from a poorly documented scheme where the mapping
of unified architectural register indices to register
classes is hardcoded all over to one where there's an
enum for the register classes and a function that
encapsulates the mapping.

3 files changed, 88 insertions, 42 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 2c6b49d82..233d532dd 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -59,6 +60,7 @@
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/quiesce_event.hh"
+#include "cpu/reg_class.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Activity.hh"
@@ -1257,16 +1259,23 @@ InOrderCPU::getPipeStage(int stage_num)
 RegIndex
 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
 {
-    if (reg_idx < FP_Base_DepTag) {
+    RegIndex rel_idx;
+
+    switch (regIdxToClass(reg_idx, &rel_idx)) {
+      case IntRegClass:
         reg_type = IntType;
-        return isa[tid]->flattenIntIndex(reg_idx);
-    } else if (reg_idx < Ctrl_Base_DepTag) {
+        return isa[tid]->flattenIntIndex(rel_idx);
+
+      case FloatRegClass:
         reg_type = FloatType;
-        reg_idx -= FP_Base_DepTag;
-        return isa[tid]->flattenFloatIndex(reg_idx);
-    } else {
+        return isa[tid]->flattenFloatIndex(rel_idx);
+
+      case MiscRegClass:
         reg_type = MiscType;
-        return reg_idx - TheISA::Ctrl_Base_DepTag;
+        return rel_idx;
+
+      default:
+        panic("register %d out of range\n", reg_idx);
     }
 }
 
@@ -1344,18 +1353,25 @@ InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
         tid = TheISA::getTargetThread(tcBase(tid));
     }
 
-    if (reg_idx < FP_Base_DepTag) {                   
+    RegIndex rel_idx;
+
+    switch (regIdxToClass(reg_idx, &rel_idx)) {
+      case IntRegClass:
         // Integer Register File
-        return readIntReg(reg_idx, tid);
-    } else if (reg_idx < Ctrl_Base_DepTag) {          
+        return readIntReg(rel_idx, tid);
+
+      case FloatRegClass:
         // Float Register File
-        reg_idx -= FP_Base_DepTag;
-        return readFloatRegBits(reg_idx, tid);
-    } else {
-        reg_idx -= Ctrl_Base_DepTag;
-        return readMiscReg(reg_idx, tid);  // Misc. Register File
+        return readFloatRegBits(rel_idx, tid);
+
+      case MiscRegClass:
+        return readMiscReg(rel_idx, tid);  // Misc. Register File
+
+      default:
+        panic("register %d out of range\n", reg_idx);
     }
 }
+
 void
 InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
                               ThreadID tid)
@@ -1365,14 +1381,20 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
         tid = TheISA::getTargetThread(tcBase(tid));
     }
 
-    if (reg_idx < FP_Base_DepTag) {            // Integer Register File
-        setIntReg(reg_idx, val, tid);
-    } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
-        reg_idx -= FP_Base_DepTag;
-        setFloatRegBits(reg_idx, val, tid);
-    } else {
-        reg_idx -= Ctrl_Base_DepTag;
-        setMiscReg(reg_idx, val, tid); // Misc. Register File
+    RegIndex rel_idx;
+
+    switch (regIdxToClass(reg_idx, &rel_idx)) {
+      case IntRegClass:
+        setIntReg(rel_idx, val, tid);
+        break;
+
+      case FloatRegClass:
+        setFloatRegBits(rel_idx, val, tid);
+        break;
+
+      case MiscRegClass:
+        setMiscReg(rel_idx, val, tid); // Misc. Register File
+        break;
     }
 }
 
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index e69c9d47b..6f189f8c9 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2012-2013 ARM Limited
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -65,6 +66,7 @@
 #include "cpu/o3/rename_map.hh"
 #include "cpu/activity.hh"
 #include "cpu/base.hh"
+#include "cpu/reg_class.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/timebuf.hh"
 #include "mem/packet.hh"
@@ -599,12 +601,19 @@ class InOrderCPU : public BaseCPU
 
     RegType inline getRegType(RegIndex reg_idx)
     {
-        if (reg_idx < TheISA::FP_Base_DepTag)
+        switch (regIdxToClass(reg_idx)) {
+          case IntRegClass:
             return IntType;
-        else if (reg_idx < TheISA::Ctrl_Base_DepTag)
+
+          case FloatRegClass:
             return FloatType;
-        else
+
+          case MiscRegClass:
             return MiscType;
+
+          default:
+            panic("register %d out of range\n", reg_idx);
+        }
     }
 
     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index dcf0ce6ae..c2765a3ba 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -42,6 +43,7 @@
 #include "cpu/inorder/cpu.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/reg_class.hh"
 #include "debug/InOrderDynInst.hh"
 #include "mem/request.hh"
 #include "sim/fault_fwd.hh"
@@ -473,14 +475,21 @@ InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
     }
 
-    if (reg_idx < FP_Base_DepTag) {                   // Integer Register File
-        return this->cpu->readIntReg(reg_idx, tid);
-    } else if (reg_idx < Ctrl_Base_DepTag) {          // Float Register File
-        reg_idx -= FP_Base_DepTag;
-        return this->cpu->readFloatRegBits(reg_idx, tid);
-    } else {
-        reg_idx -= Ctrl_Base_DepTag;
-        return this->cpu->readMiscReg(reg_idx, tid);  // Misc. Register File
+    RegIndex rel_idx;
+
+    switch (regIdxToClass(reg_idx, &rel_idx)) {
+      case IntRegClass:
+        return this->cpu->readIntReg(rel_idx, tid);
+
+      case FloatRegClass:
+        return this->cpu->readFloatRegBits(rel_idx, tid);
+
+      case MiscRegClass:
+        return this->cpu->readMiscReg(rel_idx, tid);  // Misc. Register File
+
+      default:
+        panic("register %d out of range\n", reg_idx);
+
     }
 }
 
@@ -542,14 +551,20 @@ InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
     }
 
-    if (reg_idx < FP_Base_DepTag) {            // Integer Register File
-        this->cpu->setIntReg(reg_idx, val, tid);
-    } else if (reg_idx < Ctrl_Base_DepTag) {   // Float Register File
-        reg_idx -= FP_Base_DepTag;
-        this->cpu->setFloatRegBits(reg_idx, val, tid);
-    } else {
-        reg_idx -= Ctrl_Base_DepTag;
-        this->cpu->setMiscReg(reg_idx, val, tid); // Misc. Register File
+    RegIndex rel_idx;
+
+    switch (regIdxToClass(reg_idx, &rel_idx)) {
+      case IntRegClass:
+        this->cpu->setIntReg(rel_idx, val, tid);
+        break;
+
+      case FloatRegClass:
+        this->cpu->setFloatRegBits(rel_idx, val, tid);
+        break;
+
+      case MiscRegClass:
+        this->cpu->setMiscReg(rel_idx, val, tid); // Misc. Register File
+        break;
     }
 }