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author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:37 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:37 -0400 |
commit | a444133e7359e258a20d32f7f0cc22fa07d87945 (patch) | |
tree | c15553f917d135d1be3ac66049451face641e1aa /src/cpu/inorder | |
parent | 89d0f95bf02489ab8fed382af2f104c4788b8db6 (diff) | |
download | gem5-a444133e7359e258a20d32f7f0cc22fa07d87945.tar.xz |
inorder: support for compare and swap insts
dont treat read() and write() fields as mut. exclusive
Diffstat (limited to 'src/cpu/inorder')
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 1050713a1..0da4e968e 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -833,9 +833,17 @@ CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res, Packet::Broadcast, cache_req->instIdx); - if (cache_req->dataPkt->isRead()) { + bool is_read = cache_req->dataPkt->isRead(); + bool is_write = cache_req->dataPkt->isWrite(); + + //@note: a compare and swap will both marked both read and write + if (is_read && !is_write) { + DPRINTF(InOrderCachePort, "Read Data Set in Packet\n"); + cache_req->dataPkt->dataStatic(cache_req->reqData); - } else if (cache_req->dataPkt->isWrite()) { + } + + if (is_write) { if (inst->split2ndAccess) { cache_req->dataPkt->dataStatic(inst->split2ndStoreDataPtr); } else { @@ -858,7 +866,7 @@ CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res, Request *memReq = cache_req->dataPkt->req; - if (cache_req->dataPkt->isWrite() && cache_req->memReq->isLLSC()) { + if (is_write && cache_req->memReq->isLLSC()) { assert(cache_req->inst->isStoreConditional()); DPRINTF(InOrderCachePort, "Evaluating Store Conditional access\n"); do_access = TheISA::handleLockedWrite(cpu, memReq); |