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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | 0cb180ea0dcece9157ad71b4136d557c2dbcf209 (patch) | |
| tree | f65b3376cfe8cdad517f6a2a3a8c9e2cf69c987a /src/cpu/inorder | |
| parent | 25884a87733cd35ef6613aaef9a8a08194267552 (diff) | |
| download | gem5-0cb180ea0dcece9157ad71b4136d557c2dbcf209.tar.xz | |
Registers: Eliminate the ISA defined floating point register file.
Diffstat (limited to 'src/cpu/inorder')
| -rw-r--r-- | src/cpu/inorder/cpu.cc | 10 | ||||
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 5 |
2 files changed, 9 insertions, 6 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index fc8723829..248e78314 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -265,7 +265,7 @@ InOrderCPU::InOrderCPU(Params *params) lastSquashCycle[tid] = 0; intRegFile[tid].clear(); - floatRegFile[tid].clear(); + memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid])); isa[tid].clear(); isa[tid].expandForMultithreading(numThreads, numVirtProcs); @@ -892,13 +892,13 @@ InOrderCPU::readIntReg(int reg_idx, ThreadID tid) FloatReg InOrderCPU::readFloatReg(int reg_idx, ThreadID tid) { - return floatRegFile[tid].readReg(reg_idx); + return floatRegs.f[tid][reg_idx]; } FloatRegBits InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid) {; - return floatRegFile[tid].readRegBits(reg_idx); + return floatRegs.i[tid][reg_idx]; } void @@ -911,14 +911,14 @@ InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid) void InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid) { - floatRegFile[tid].setReg(reg_idx, val); + floatRegs.f[tid][reg_idx] = val; } void InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid) { - floatRegFile[tid].setRegBits(reg_idx, val); + floatRegs.i[tid][reg_idx] = val; } uint64_t diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index bda4c41bd..f4cc72e9c 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -259,7 +259,10 @@ class InOrderCPU : public BaseCPU /** The Register File for the CPU */ TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];; - TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];; + union { + FloatReg f[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; + FloatRegBits i[ThePipeline::MaxThreads][TheISA::NumFloatRegs]; + } floatRegs; /** ISA state */ TheISA::ISA isa[ThePipeline::MaxThreads]; |