types: add a type for thread IDs and try to use it everywhere

39 files changed, 433 insertions, 420 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index e901b475e..24483bf25 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -29,9 +29,10 @@
  *
  */
 
-#include "config/full_system.hh"
+#include <algorithm>
 
 #include "arch/utility.hh"
+#include "config/full_system.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/activity.hh"
 #include "cpu/simple_thread.hh"
@@ -49,7 +50,6 @@
 #include "mem/translating_port.hh"
 #include "sim/process.hh"
 #include "sim/stat_control.hh"
-#include <algorithm>
 
 using namespace std;
 using namespace TheISA;
@@ -74,7 +74,7 @@ InOrderCPU::TickEvent::description()
 }
 
 InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
-                             Fault fault, unsigned _tid, unsigned _vpe)
+                             Fault fault, ThreadID _tid, unsigned _vpe)
     : Event(CPU_Tick_Pri), cpu(_cpu)
 {
     setEvent(e_type, fault, _tid, _vpe);
@@ -175,7 +175,6 @@ InOrderCPU::InOrderCPU(Params *params)
       switchCount(0),
       deferRegistration(false/*params->deferRegistration*/),
       stageTracing(params->stageTracing),
-      numThreads(params->numThreads),
       numVirtProcs(1)
 {
     cpu_params = params;
@@ -204,28 +203,28 @@ InOrderCPU::InOrderCPU(Params *params)
         fatal("Unable to find port for data.\n");
     }
 
-    for (int i = 0; i < numThreads; ++i) {
-        if (i < params->workload.size()) {
+    for (ThreadID tid = 0; tid < numThreads; ++tid) {
+        if (tid < params->workload.size()) {
             DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
-                    i, this->thread[i]);
-            this->thread[i] = new Thread(this, i, params->workload[i],
-                                         i);
+                    tid, this->thread[tid]);
+            this->thread[tid] =
+                new Thread(this, tid, params->workload[tid], tid);
         } else {
             //Allocate Empty thread so M5 can use later
             //when scheduling threads to CPU
             Process* dummy_proc = params->workload[0];
-            this->thread[i] = new Thread(this, i, dummy_proc, i);
+            this->thread[tid] = new Thread(this, tid, dummy_proc, tid);
         }
 
         // Setup the TC that will serve as the interface to the threads/CPU.
         InOrderThreadContext *tc = new InOrderThreadContext;
         tc->cpu = this;
-        tc->thread = this->thread[i];
+        tc->thread = thread[tid];
 
         // Give the thread the TC.
-        thread[i]->tc = tc;
-        thread[i]->setFuncExeInst(0);
-        globalSeqNum[i] = 1;
+        thread[tid]->tc = tc;
+        thread[tid]->setFuncExeInst(0);
+        globalSeqNum[tid] = 1;
 
         // Add the TC to the CPU's list of TC's.
         this->threadContexts.push_back(tc);
@@ -257,7 +256,7 @@ InOrderCPU::InOrderCPU(Params *params)
     }
 
     // Initialize thread specific variables
-    for (int tid=0; tid < numThreads; tid++) {
+    for (ThreadID tid = 0; tid < numThreads; tid++) {
         archRegDepMap[tid].setCPU(this);
 
         nonSpecInstActive[tid] = false;
@@ -434,19 +433,19 @@ InOrderCPU::init()
 
     // Set inSyscall so that the CPU doesn't squash when initially
     // setting up registers.
-    for (int i = 0; i < number_of_threads; ++i)
-        thread[i]->inSyscall = true;
+    for (ThreadID tid = 0; tid < numThreads; ++tid)
+        thread[tid]->inSyscall = true;
 
 #if FULL_SYSTEM
-    for (int tid=0; tid < number_of_threads; tid++) {
+    for (ThreadID tid = 0; tid < numThreads; tid++) {
         ThreadContext *src_tc = threadContexts[tid];
         TheISA::initCPU(src_tc, src_tc->contextId());
     }
 #endif
 
     // Clear inSyscall.
-    for (int i = 0; i < number_of_threads; ++i)
-        thread[i]->inSyscall = false;
+    for (ThreadID tid = 0; tid < numThreads; ++tid)
+        thread[tid]->inSyscall = false;
 
     // Call Initializiation Routine for Resource Pool
     resPool->init();
@@ -472,21 +471,21 @@ InOrderCPU::getPort(const std::string &if_name, int idx)
 }
 
 void
-InOrderCPU::trap(Fault fault, unsigned tid, int delay)
+InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
 {
     //@ Squash Pipeline during TRAP
     scheduleCpuEvent(Trap, fault, tid, 0/*vpe*/, delay);
 }
 
 void
-InOrderCPU::trapCPU(Fault fault, unsigned tid)
+InOrderCPU::trapCPU(Fault fault, ThreadID tid)
 {
     fault->invoke(tcBase(tid));
 }
 
 void
 InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
-                           unsigned tid, unsigned vpe, unsigned delay)
+                           ThreadID tid, unsigned vpe, unsigned delay)
 {
     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, vpe);
 
@@ -500,26 +499,27 @@ InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
     }
 
     // Broadcast event to the Resource Pool
-    DynInstPtr dummy_inst = new InOrderDynInst(this, NULL, getNextEventNum(), tid);
+    DynInstPtr dummy_inst =
+        new InOrderDynInst(this, NULL, getNextEventNum(), tid);
     resPool->scheduleEvent(c_event, dummy_inst, 0, 0, tid);
 }
 
 inline bool
-InOrderCPU::isThreadActive(unsigned tid)
+InOrderCPU::isThreadActive(ThreadID tid)
 {
-  list<unsigned>::iterator isActive = std::find(
-        activeThreads.begin(), activeThreads.end(), tid);
+  list<ThreadID>::iterator isActive =
+      std::find(activeThreads.begin(), activeThreads.end(), tid);
 
     return (isActive != activeThreads.end());
 }
 
 
 void
-InOrderCPU::activateThread(unsigned tid)
+InOrderCPU::activateThread(ThreadID tid)
 {
     if (!isThreadActive(tid)) {
-        DPRINTF(InOrderCPU, "Adding Thread %i to active threads list in CPU.\n",
-                tid);
+        DPRINTF(InOrderCPU,
+                "Adding Thread %i to active threads list in CPU.\n", tid);
         activeThreads.push_back(tid);
 
         wakeCPU();
@@ -527,15 +527,15 @@ InOrderCPU::activateThread(unsigned tid)
 }
 
 void
-InOrderCPU::deactivateThread(unsigned tid)
+InOrderCPU::deactivateThread(ThreadID tid)
 {
     DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
 
     if (isThreadActive(tid)) {
         DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
                 tid);
-        list<unsigned>::iterator thread_it = std::find(activeThreads.begin(),
-                                                 activeThreads.end(), tid);
+        list<ThreadID>::iterator thread_it =
+            std::find(activeThreads.begin(), activeThreads.end(), tid);
 
         removePipelineStalls(*thread_it);
 
@@ -546,7 +546,7 @@ InOrderCPU::deactivateThread(unsigned tid)
 }
 
 void
-InOrderCPU::removePipelineStalls(unsigned tid)
+InOrderCPU::removePipelineStalls(ThreadID tid)
 {
     DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
             tid);
@@ -557,16 +557,16 @@ InOrderCPU::removePipelineStalls(unsigned tid)
 
 }
 bool
-InOrderCPU::isThreadInCPU(unsigned tid)
+InOrderCPU::isThreadInCPU(ThreadID tid)
 {
-  list<unsigned>::iterator isCurrent = std::find(
-        currentThreads.begin(), currentThreads.end(), tid);
+  list<ThreadID>::iterator isCurrent =
+      std::find(currentThreads.begin(), currentThreads.end(), tid);
 
     return (isCurrent != currentThreads.end());
 }
 
 void
-InOrderCPU::addToCurrentThreads(unsigned tid)
+InOrderCPU::addToCurrentThreads(ThreadID tid)
 {
     if (!isThreadInCPU(tid)) {
         DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU.\n",
@@ -576,22 +576,22 @@ InOrderCPU::addToCurrentThreads(unsigned tid)
 }
 
 void
-InOrderCPU::removeFromCurrentThreads(unsigned tid)
+InOrderCPU::removeFromCurrentThreads(ThreadID tid)
 {
     if (isThreadInCPU(tid)) {
-        DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU.\n",
-                tid);
-        list<unsigned>::iterator isCurrent = std::find(
-            currentThreads.begin(), currentThreads.end(), tid);
+        DPRINTF(InOrderCPU,
+                "Adding Thread %i to current threads list in CPU.\n", tid);
+        list<ThreadID>::iterator isCurrent =
+            std::find(currentThreads.begin(), currentThreads.end(), tid);
         currentThreads.erase(isCurrent);
     }
 }
 
 bool
-InOrderCPU::isThreadSuspended(unsigned tid)
+InOrderCPU::isThreadSuspended(ThreadID tid)
 {
-  list<unsigned>::iterator isSuspended = std::find(
-        suspendedThreads.begin(), suspendedThreads.end(), tid);
+  list<ThreadID>::iterator isSuspended =
+      std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
 
     return (isSuspended!= suspendedThreads.end());
 }
@@ -612,7 +612,7 @@ InOrderCPU::enableVPEs(unsigned vpe)
     DPRINTF(InOrderCPU, "[vpe:%i]: Enabling Concurrent Execution "
             "virtual processors %i", vpe);
 
-    list<unsigned>::iterator thread_it = currentThreads.begin();
+    list<ThreadID>::iterator thread_it = currentThreads.begin();
 
     while (thread_it != currentThreads.end()) {
         if (!isThreadSuspended(*thread_it)) {
@@ -623,7 +623,7 @@ InOrderCPU::enableVPEs(unsigned vpe)
 }
 
 void
-InOrderCPU::disableVirtProcElement(unsigned tid, unsigned vpe)
+InOrderCPU::disableVirtProcElement(ThreadID tid, unsigned vpe)
 {
     DPRINTF(InOrderCPU, "[vpe:%i]: Scheduling  "
             "Disabling of concurrent virtual processor execution",
@@ -633,16 +633,16 @@ InOrderCPU::disableVirtProcElement(unsigned tid, unsigned vpe)
 }
 
 void
-InOrderCPU::disableVPEs(unsigned tid, unsigned vpe)
+InOrderCPU::disableVPEs(ThreadID tid, unsigned vpe)
 {
     DPRINTF(InOrderCPU, "[vpe:%i]: Disabling Concurrent Execution of "
             "virtual processors %i", vpe);
 
     unsigned base_vpe = TheISA::getVirtProcNum(tcBase(tid));
 
-    list<unsigned>::iterator thread_it = activeThreads.begin();
+    list<ThreadID>::iterator thread_it = activeThreads.begin();
 
-    std::vector<list<unsigned>::iterator> removeList;
+    vector<list<ThreadID>::iterator> removeList;
 
     while (thread_it != activeThreads.end()) {
         if (base_vpe != vpe) {
@@ -672,7 +672,7 @@ InOrderCPU::enableThreads(unsigned vpe)
     DPRINTF(InOrderCPU, "[vpe:%i]: Enabling Multithreading on "
             "virtual processor %i", vpe);
 
-    list<unsigned>::iterator thread_it = currentThreads.begin();
+    list<ThreadID>::iterator thread_it = currentThreads.begin();
 
     while (thread_it != currentThreads.end()) {
         if (TheISA::getVirtProcNum(tcBase(*thread_it)) == vpe) {
@@ -684,7 +684,7 @@ InOrderCPU::enableThreads(unsigned vpe)
     }
 }
 void
-InOrderCPU::disableMultiThreading(unsigned tid, unsigned vpe)
+InOrderCPU::disableMultiThreading(ThreadID tid, unsigned vpe)
 {
     // Schedule event to take place at end of cycle
    DPRINTF(InOrderCPU, "[tid:%i]: Scheduling Disable Multithreading on "
@@ -694,14 +694,14 @@ InOrderCPU::disableMultiThreading(unsigned tid, unsigned vpe)
 }
 
 void
-InOrderCPU::disableThreads(unsigned tid, unsigned vpe)
+InOrderCPU::disableThreads(ThreadID tid, unsigned vpe)
 {
     DPRINTF(InOrderCPU, "[tid:%i]: Disabling Multithreading on "
             "virtual processor %i", tid, vpe);
 
-    list<unsigned>::iterator thread_it = activeThreads.begin();
+    list<ThreadID>::iterator thread_it = activeThreads.begin();
 
-    std::vector<list<unsigned>::iterator> removeList;
+    vector<list<ThreadID>::iterator> removeList;
 
     while (thread_it != activeThreads.end()) {
         if (TheISA::getVirtProcNum(tcBase(*thread_it)) == vpe) {
@@ -722,8 +722,8 @@ InOrderCPU::updateThreadPriority()
     {
         //DEFAULT TO ROUND ROBIN SCHEME
         //e.g. Move highest priority to end of thread list
-        list<unsigned>::iterator list_begin = activeThreads.begin();
-        list<unsigned>::iterator list_end   = activeThreads.end();
+        list<ThreadID>::iterator list_begin = activeThreads.begin();
+        list<ThreadID>::iterator list_end   = activeThreads.end();
 
         unsigned high_thread = *list_begin;
 
@@ -737,7 +737,7 @@ inline void
 InOrderCPU::tickThreadStats()
 {
     /** Keep track of cycles that each thread is active */
-    list<unsigned>::iterator thread_it = activeThreads.begin();
+    list<ThreadID>::iterator thread_it = activeThreads.begin();
     while (thread_it != activeThreads.end()) {
         threadCycles[*thread_it]++;
         thread_it++;
@@ -750,7 +750,7 @@ InOrderCPU::tickThreadStats()
 }
 
 void
-InOrderCPU::activateContext(unsigned tid, int delay)
+InOrderCPU::activateContext(ThreadID tid, int delay)
 {
     DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
 
@@ -765,27 +765,27 @@ InOrderCPU::activateContext(unsigned tid, int delay)
 
 
 void
-InOrderCPU::suspendContext(unsigned tid, int delay)
+InOrderCPU::suspendContext(ThreadID tid, int delay)
 {
     scheduleCpuEvent(SuspendThread, NoFault, tid, 0/*vpe*/, delay);
     //_status = Idle;
 }
 
 void
-InOrderCPU::suspendThread(unsigned tid)
+InOrderCPU::suspendThread(ThreadID tid)
 {
     DPRINTF(InOrderCPU,"[tid: %i]: Suspended ...\n", tid);
     deactivateThread(tid);
 }
 
 void
-InOrderCPU::deallocateContext(unsigned tid, int delay)
+InOrderCPU::deallocateContext(ThreadID tid, int delay)
 {
     scheduleCpuEvent(DeallocateThread, NoFault, tid, 0/*vpe*/, delay);
 }
 
 void
-InOrderCPU::deallocateThread(unsigned tid)
+InOrderCPU::deallocateThread(ThreadID tid)
 {
     DPRINTF(InOrderCPU,"[tid:%i]: Deallocating ...", tid);
 
@@ -797,7 +797,7 @@ InOrderCPU::deallocateThread(unsigned tid)
 }
 
 void
-InOrderCPU::squashThreadInPipeline(unsigned tid)
+InOrderCPU::squashThreadInPipeline(ThreadID tid)
 {
     //Squash all instructions in each stage
     for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
@@ -806,7 +806,7 @@ InOrderCPU::squashThreadInPipeline(unsigned tid)
 }
 
 void
-InOrderCPU::haltContext(unsigned tid, int delay)
+InOrderCPU::haltContext(ThreadID tid, int delay)
 {
     DPRINTF(InOrderCPU, "[tid:%i]: Halt context called.\n", tid);
 
@@ -817,13 +817,13 @@ InOrderCPU::haltContext(unsigned tid, int delay)
 }
 
 void
-InOrderCPU::insertThread(unsigned tid)
+InOrderCPU::insertThread(ThreadID tid)
 {
     panic("Unimplemented Function\n.");
 }
 
 void
-InOrderCPU::removeThread(unsigned tid)
+InOrderCPU::removeThread(ThreadID tid)
 {
     DPRINTF(InOrderCPU, "Removing Thread %i from CPU.\n", tid);
 
@@ -838,97 +838,98 @@ InOrderCPU::getPipeStage(int stage_num)
 
 
 void
-InOrderCPU::activateWhenReady(int tid)
+InOrderCPU::activateWhenReady(ThreadID tid)
 {
     panic("Unimplemented Function\n.");
 }
 
 
 uint64_t
-InOrderCPU::readPC(unsigned tid)
+InOrderCPU::readPC(ThreadID tid)
 {
     return PC[tid];
 }
 
 
 void
-InOrderCPU::setPC(Addr new_PC, unsigned tid)
+InOrderCPU::setPC(Addr new_PC, ThreadID tid)
 {
     PC[tid] = new_PC;
 }
 
 
 uint64_t
-InOrderCPU::readNextPC(unsigned tid)
+InOrderCPU::readNextPC(ThreadID tid)
 {
     return nextPC[tid];
 }
 
 
 void
-InOrderCPU::setNextPC(uint64_t new_NPC, unsigned tid)
+InOrderCPU::setNextPC(uint64_t new_NPC, ThreadID tid)
 {
     nextPC[tid] = new_NPC;
 }
 
 
 uint64_t
-InOrderCPU::readNextNPC(unsigned tid)
+InOrderCPU::readNextNPC(ThreadID tid)
 {
     return nextNPC[tid];
 }
 
 
 void
-InOrderCPU::setNextNPC(uint64_t new_NNPC, unsigned tid)
+InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid)
 {
     nextNPC[tid] = new_NNPC;
 }
 
 uint64_t
-InOrderCPU::readIntReg(int reg_idx, unsigned tid)
+InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
 {
     return intRegFile[tid].readReg(reg_idx);
 }
 
 FloatReg
-InOrderCPU::readFloatReg(int reg_idx, unsigned tid, int width)
+InOrderCPU::readFloatReg(int reg_idx, ThreadID tid, int width)
 {
 
     return floatRegFile[tid].readReg(reg_idx, width);
 }
 
 FloatRegBits
-InOrderCPU::readFloatRegBits(int reg_idx, unsigned tid, int width)
+InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid, int width)
 {;
     return floatRegFile[tid].readRegBits(reg_idx, width);
 }
 
 void
-InOrderCPU::setIntReg(int reg_idx, uint64_t val, unsigned tid)
+InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
 {
     intRegFile[tid].setReg(reg_idx, val);
 }
 
 
 void
-InOrderCPU::setFloatReg(int reg_idx, FloatReg val, unsigned tid, int width)
+InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid, int width)
 {
     floatRegFile[tid].setReg(reg_idx, val, width);
 }
 
 
 void
-InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, unsigned tid, int width)
+InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid,
+                            int width)
 {
     floatRegFile[tid].setRegBits(reg_idx, val, width);
 }
 
 uint64_t
-InOrderCPU::readRegOtherThread(unsigned reg_idx, unsigned tid)
+InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
 {
     // If Default value is set, then retrieve target thread
-    if (tid == -1) {
+    if (tid == InvalidThreadID) {
         tid = TheISA::getTargetThread(tcBase(tid));
     }
 
@@ -943,10 +944,11 @@ InOrderCPU::readRegOtherThread(unsigned reg_idx, unsigned tid)
     }
 }
 void
-InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val, unsigned tid)
+InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
+                              ThreadID tid)
 {
     // If Default value is set, then retrieve target thread
-    if (tid == -1) {
+    if (tid == InvalidThreadID) {
         tid = TheISA::getTargetThread(tcBase(tid));
     }
 
@@ -962,25 +964,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val, unsigned tid
 }
 
 MiscReg
-InOrderCPU::readMiscRegNoEffect(int misc_reg, unsigned tid)
+InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
     return miscRegFile.readRegNoEffect(misc_reg, tid);
 }
 
 MiscReg
-InOrderCPU::readMiscReg(int misc_reg, unsigned tid)
+InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
 {
     return miscRegFile.readReg(misc_reg, tcBase(tid), tid);
 }
 
 void
-InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
+InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 {
     miscRegFile.setRegNoEffect(misc_reg, val, tid);
 }
 
 void
-InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
+InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
 {
     miscRegFile.setReg(misc_reg, val, tcBase(tid), tid);
 }
@@ -989,7 +991,7 @@ InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
 InOrderCPU::ListIt
 InOrderCPU::addInst(DynInstPtr &inst)
 {
-    int tid = inst->readTid();
+    ThreadID tid = inst->readTid();
 
     instList[tid].push_back(inst);
 
@@ -997,7 +999,7 @@ InOrderCPU::addInst(DynInstPtr &inst)
 }
 
 void
-InOrderCPU::instDone(DynInstPtr inst, unsigned tid)
+InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
 {
     // Set the CPU's PCs - This contributes to the precise state of the CPU which can be used
     // when restoring a thread to the CPU after a fork or after an exception
@@ -1069,8 +1071,7 @@ InOrderCPU::removeInst(DynInstPtr &inst)
 }
 
 void
-InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num,
-                                  unsigned tid)
+InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
 {
     //assert(!instList[tid].empty());
 
@@ -1099,7 +1100,7 @@ InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num,
 
 
 inline void
-InOrderCPU::squashInstIt(const ListIt &instIt, const unsigned &tid)
+InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
 {
     if ((*instIt)->threadNumber == tid) {
         DPRINTF(InOrderCPU, "Squashing instruction, "
@@ -1126,7 +1127,7 @@ InOrderCPU::cleanUpRemovedInsts()
                 (*removeList.front())->readPC());
 
         DynInstPtr inst = *removeList.front();
-        int tid = inst->threadNumber;
+        ThreadID tid = inst->threadNumber;
 
         // Make Sure Resource Schedule Is Emptied Out
         ThePipeline::ResSchedule *inst_sched = &inst->resSched;
@@ -1234,7 +1235,7 @@ InOrderCPU::wakeCPU()
 }
 
 void
-InOrderCPU::syscall(int64_t callnum, int tid)
+InOrderCPU::syscall(int64_t callnum, ThreadID tid)
 {
     DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
 
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 55b04f6a9..faf37382f 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -41,6 +41,7 @@
 #include "arch/isa_traits.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
+#include "base/types.hh"
 #include "config/full_system.hh"
 #include "cpu/activity.hh"
 #include "cpu/base.hh"
@@ -185,17 +186,18 @@ class InOrderCPU : public BaseCPU
 
       public:
         CPUEventType cpuEventType;
-        unsigned tid;
+        ThreadID tid;
         unsigned vpe;
         Fault fault;
 
       public:
         /** Constructs a CPU event. */
         CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
-                 unsigned _tid, unsigned _vpe);
+                 ThreadID _tid, unsigned _vpe);
 
         /** Set Type of Event To Be Scheduled */
-        void setEvent(CPUEventType e_type, Fault _fault, unsigned _tid, unsigned _vpe)
+        void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
+                      unsigned _vpe)
         {
             fault = _fault;
             cpuEventType = e_type;
@@ -217,7 +219,7 @@ class InOrderCPU : public BaseCPU
     };
 
     /** Schedule a CPU Event */
-    void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, unsigned tid,
+    void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
                           unsigned vpe, unsigned delay = 0);
 
   public:
@@ -293,29 +295,29 @@ class InOrderCPU : public BaseCPU
     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
      *  trapCPU() - Traps to handle given fault
      */
-    void trap(Fault fault, unsigned tid, int delay = 0);
-    void trapCPU(Fault fault, unsigned tid);
+    void trap(Fault fault, ThreadID tid, int delay = 0);
+    void trapCPU(Fault fault, ThreadID tid);
 
     /** Setup CPU to insert a thread's context */
-    void insertThread(unsigned tid);
+    void insertThread(ThreadID tid);
 
     /** Remove all of a thread's context from CPU */
-    void removeThread(unsigned tid);
+    void removeThread(ThreadID tid);
 
     /** Add Thread to Active Threads List. */
-    void activateContext(unsigned tid, int delay = 0);
-    void activateThread(unsigned tid);
+    void activateContext(ThreadID tid, int delay = 0);
+    void activateThread(ThreadID tid);
 
     /** Remove Thread from Active Threads List */
-    void suspendContext(unsigned tid, int delay = 0);
-    void suspendThread(unsigned tid);
+    void suspendContext(ThreadID tid, int delay = 0);
+    void suspendThread(ThreadID tid);
 
     /** Remove Thread from Active Threads List &&
      *  Remove Thread Context from CPU.
      */
-    void deallocateContext(unsigned tid, int delay = 0);
-    void deallocateThread(unsigned tid);
-    void deactivateThread(unsigned tid);
+    void deallocateContext(ThreadID tid, int delay = 0);
+    void deallocateThread(ThreadID tid);
+    void deactivateThread(ThreadID tid);
 
     PipelineStage* getPipeStage(int stage_num);
 
@@ -329,30 +331,30 @@ class InOrderCPU : public BaseCPU
     /** Remove Thread from Active Threads List &&
      *  Remove Thread Context from CPU.
      */
-    void haltContext(unsigned tid, int delay = 0);
+    void haltContext(ThreadID tid, int delay = 0);
 
-    void removePipelineStalls(unsigned tid);
+    void removePipelineStalls(ThreadID tid);
 
-    void squashThreadInPipeline(unsigned tid);
+    void squashThreadInPipeline(ThreadID tid);
 
     /// Notify the CPU to enable a virtual processor element.
     virtual void enableVirtProcElement(unsigned vpe);
     void enableVPEs(unsigned vpe);
 
     /// Notify the CPU to disable a virtual processor element.
-    virtual void disableVirtProcElement(unsigned tid, unsigned vpe);
-    void disableVPEs(unsigned tid, unsigned vpe);
+    virtual void disableVirtProcElement(ThreadID tid, unsigned vpe);
+    void disableVPEs(ThreadID tid, unsigned vpe);
 
     /// Notify the CPU that multithreading is enabled.
     virtual void enableMultiThreading(unsigned vpe);
     void enableThreads(unsigned vpe);
 
     /// Notify the CPU that multithreading is disabled.
-    virtual void disableMultiThreading(unsigned tid, unsigned vpe);
-    void disableThreads(unsigned tid, unsigned vpe);
+    virtual void disableMultiThreading(ThreadID tid, unsigned vpe);
+    void disableThreads(ThreadID tid, unsigned vpe);
 
     /** Activate a Thread When CPU Resources are Available. */
-    void activateWhenReady(int tid);
+    void activateWhenReady(ThreadID tid);
 
     /** Add or Remove a Thread Context in the CPU. */
     void doContextSwitch();
@@ -365,19 +367,19 @@ class InOrderCPU : public BaseCPU
     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 
     /** Get the current instruction sequence number, and increment it. */
-    InstSeqNum getAndIncrementInstSeq(unsigned tid)
+    InstSeqNum getAndIncrementInstSeq(ThreadID tid)
     { return globalSeqNum[tid]++; }
 
     /** Get the current instruction sequence number, and increment it. */
-    InstSeqNum nextInstSeqNum(unsigned tid)
+    InstSeqNum nextInstSeqNum(ThreadID tid)
     { return globalSeqNum[tid]; }
 
     /** Increment Instruction Sequence Number */
-    void incrInstSeqNum(unsigned tid)
+    void incrInstSeqNum(ThreadID tid)
     { globalSeqNum[tid]++; }
 
     /** Set Instruction Sequence Number */
-    void setInstSeqNum(unsigned tid, InstSeqNum seq_num)
+    void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
     {
         globalSeqNum[tid] = seq_num;
     }
@@ -389,73 +391,76 @@ class InOrderCPU : public BaseCPU
     }
 
     /** Get instruction asid. */
-    int getInstAsid(unsigned tid)
+    int getInstAsid(ThreadID tid)
     { return thread[tid]->getInstAsid(); }
 
     /** Get data asid. */
-    int getDataAsid(unsigned tid)
+    int getDataAsid(ThreadID tid)
     { return thread[tid]->getDataAsid(); }
 
     /** Register file accessors  */
-    uint64_t readIntReg(int reg_idx, unsigned tid);
+    uint64_t readIntReg(int reg_idx, ThreadID tid);
 
-    FloatReg readFloatReg(int reg_idx, unsigned tid,
+    FloatReg readFloatReg(int reg_idx, ThreadID tid,
                           int width = TheISA::SingleWidth);
 
-    FloatRegBits readFloatRegBits(int reg_idx, unsigned tid,
+    FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid,
                                   int width = TheISA::SingleWidth);
 
-    void setIntReg(int reg_idx, uint64_t val, unsigned tid);
+    void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
 
-    void setFloatReg(int reg_idx, FloatReg val,  unsigned tid,
+    void setFloatReg(int reg_idx, FloatReg val, ThreadID tid,
                      int width = TheISA::SingleWidth);
 
-    void setFloatRegBits(int reg_idx, FloatRegBits val,  unsigned tid,
+    void setFloatRegBits(int reg_idx, FloatRegBits val,  ThreadID tid,
                          int width = TheISA::SingleWidth);
 
     /** Reads a miscellaneous register. */
-    MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0);
+    MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscReg(int misc_reg, unsigned tid = 0);
+    MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
 
     /** Sets a miscellaneous register. */
-    void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
+    void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
+                            ThreadID tid = 0);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0);
+    void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
 
     /** Reads a int/fp/misc reg. from another thread depending on ISA-defined
      *  target thread
      */
-    uint64_t readRegOtherThread(unsigned misc_reg, unsigned tid = -1);
+    uint64_t readRegOtherThread(unsigned misc_reg,
+                                ThreadID tid = InvalidThreadID);
 
     /** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
      * target thread
      */
-    void setRegOtherThread(unsigned misc_reg, const MiscReg &val, unsigned tid);
+    void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
+                           ThreadID tid);
 
     /** Reads the commit PC of a specific thread. */
-    uint64_t readPC(unsigned tid);
+    uint64_t readPC(ThreadID tid);
 
     /** Sets the commit PC of a specific thread. */
-    void setPC(Addr new_PC, unsigned tid);
+    void setPC(Addr new_PC, ThreadID tid);
 
     /** Reads the next PC of a specific thread. */
-    uint64_t readNextPC(unsigned tid);
+    uint64_t readNextPC(ThreadID tid);
 
     /** Sets the next PC of a specific thread. */
-    void setNextPC(uint64_t val, unsigned tid);
+    void setNextPC(uint64_t val, ThreadID tid);
 
     /** Reads the next NPC of a specific thread. */
-    uint64_t readNextNPC(unsigned tid);
+    uint64_t readNextNPC(ThreadID tid);
 
     /** Sets the next NPC of a specific thread. */
-    void setNextNPC(uint64_t val, unsigned tid);
+    void setNextNPC(uint64_t val, ThreadID tid);
 
     /** Function to add instruction onto the head of the list of the
      *  instructions.  Used when new instructions are fetched.
@@ -463,7 +468,7 @@ class InOrderCPU : public BaseCPU
     ListIt addInst(DynInstPtr &inst);
 
     /** Function to tell the CPU that an instruction has completed. */
-    void instDone(DynInstPtr inst, unsigned tid);
+    void instDone(DynInstPtr inst, ThreadID tid);
 
     /** Add Instructions to the CPU Remove List*/
     void addToRemoveList(DynInstPtr &inst);
@@ -472,10 +477,10 @@ class InOrderCPU : public BaseCPU
     void removeInst(DynInstPtr &inst);
 
     /** Remove all instructions younger than the given sequence number. */
-    void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
+    void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 
     /** Removes the instruction pointed to by the iterator. */
-    inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
+    inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 
     /** Cleans up all instructions on the instruction remove list. */
     void cleanUpRemovedInsts();
@@ -513,7 +518,7 @@ class InOrderCPU : public BaseCPU
     void writeHint(DynInstPtr inst);
 
     /** Executes a syscall.*/
-    void syscall(int64_t callnum, int tid);
+    void syscall(int64_t callnum, ThreadID tid);
 
   public:
     /** Per-Thread List of all the instructions in flight. */
@@ -553,24 +558,24 @@ class InOrderCPU : public BaseCPU
     /** Last Cycle that the CPU squashed instruction end. */
     Tick lastSquashCycle[ThePipeline::MaxThreads];
 
-    std::list<unsigned> fetchPriorityList;
+    std::list<ThreadID> fetchPriorityList;
 
   protected:
     /** Active Threads List */
-    std::list<unsigned> activeThreads;
+    std::list<ThreadID> activeThreads;
 
     /** Current Threads List */
-    std::list<unsigned> currentThreads;
+    std::list<ThreadID> currentThreads;
 
     /** Suspended Threads List */
-    std::list<unsigned> suspendedThreads;
+    std::list<ThreadID> suspendedThreads;
 
     /** Thread Status Functions (Unused Currently) */
-    bool isThreadInCPU(unsigned tid);
-    bool isThreadActive(unsigned tid);
-    bool isThreadSuspended(unsigned tid);
-    void addToCurrentThreads(unsigned tid);
-    void removeFromCurrentThreads(unsigned tid);
+    bool isThreadInCPU(ThreadID tid);
+    bool isThreadActive(ThreadID tid);
+    bool isThreadSuspended(ThreadID tid);
+    void addToCurrentThreads(ThreadID tid);
+    void removeFromCurrentThreads(ThreadID tid);
 
   private:
     /** The activity recorder; used to tell if the CPU has any
@@ -583,7 +588,7 @@ class InOrderCPU : public BaseCPU
     void readFunctional(Addr addr, uint32_t &buffer);
 
     /** Number of Active Threads in the CPU */
-    int numActiveThreads() { return activeThreads.size(); }
+    ThreadID numActiveThreads() { return activeThreads.size(); }
 
     /** Records that there was time buffer activity this cycle. */
     void activityThisCycle() { activityRec.activity(); }
@@ -600,7 +605,7 @@ class InOrderCPU : public BaseCPU
     void wakeCPU();
 
     /** Gets a free thread id. Use if thread ids change across system. */
-    int getFreeTid();
+    ThreadID getFreeTid();
 
     // LL/SC debug functionality
     unsigned stCondFails;
@@ -608,7 +613,7 @@ class InOrderCPU : public BaseCPU
     unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
 
     /** Returns a pointer to a thread context. */
-    ThreadContext *tcBase(unsigned tid = 0)
+    ThreadContext *tcBase(ThreadID tid = 0)
     {
         return thread[tid]->getTC();
     }
@@ -618,8 +623,8 @@ class InOrderCPU : public BaseCPU
     {
         Counter total(0);
 
-        for (int i=0; i < thread.size(); i++)
-            total += thread[i]->numInst;
+        for (ThreadID tid = 0; tid < thread.size(); tid++)
+            total += thread[tid]->numInst;
 
         return total;
     }
@@ -657,9 +662,6 @@ class InOrderCPU : public BaseCPU
     /** The cycle that the CPU was last running, used for statistics. */
     Tick lastRunningCycle;
 
-    /** Number of Threads the CPU can process */
-    unsigned numThreads;
-
     /** Number of Virtual Processors the CPU can process */
     unsigned numVirtProcs;
 
diff --git a/src/cpu/inorder/first_stage.cc b/src/cpu/inorder/first_stage.cc
index cc0af13f9..8bd703c56 100644
--- a/src/cpu/inorder/first_stage.cc
+++ b/src/cpu/inorder/first_stage.cc
@@ -43,7 +43,7 @@ FirstStage::FirstStage(Params *params, unsigned stage_num)
     : PipelineStage(params, stage_num), numFetchingThreads(1),
       fetchPolicy(FirstStage::RoundRobin)
 {
-    for(int tid=0; tid < this->numThreads; tid++) {
+    for(ThreadID tid = 0; tid < this->numThreads; tid++) {
         stageStatus[tid] = Running;
     }
 }
@@ -60,7 +60,7 @@ FirstStage::setCPU(InOrderCPU *cpu_ptr)
 
 
 void
-FirstStage::squash(InstSeqNum squash_seq_num, unsigned tid)
+FirstStage::squash(InstSeqNum squash_seq_num, ThreadID tid)
 {
     // Set status to squashing.
     //stageStatus[tid] = Squashing;
@@ -96,17 +96,17 @@ FirstStage::squash(InstSeqNum squash_seq_num, unsigned tid)
 void
 FirstStage::processStage(bool &status_change)
 {
-    list<unsigned>::iterator threads = (*activeThreads).begin();
+    list<ThreadID>::iterator threads = activeThreads->begin();
 
     //Check stall and squash signals.
-    while (threads != (*activeThreads).end()) {
-        unsigned tid = *threads++;
+    while (threads != activeThreads->end()) {
+        ThreadID tid = *threads++;
         status_change =  checkSignalsAndUpdate(tid) || status_change;
     }
 
     for (int threadFetched = 0; threadFetched < numFetchingThreads;
          threadFetched++) {
-        int tid = getFetchingThread(fetchPolicy);
+        ThreadID tid = getFetchingThread(fetchPolicy);
 
         if (tid >= 0) {
             DPRINTF(InOrderStage, "Processing [tid:%i]\n",tid);
@@ -120,7 +120,7 @@ FirstStage::processStage(bool &status_change)
 //@TODO: Note in documentation, that when you make a pipeline stage change, then
 //make sure you change the first stage too
 void
-FirstStage::processInsts(unsigned tid)
+FirstStage::processInsts(ThreadID tid)
 {
     bool all_reqs_completed = true;
 
@@ -194,7 +194,7 @@ FirstStage::processInsts(unsigned tid)
     }
 }
 
-int
+ThreadID
 FirstStage::getFetchingThread(FetchPriority &fetch_priority)
 {
     if (numThreads > 1) {
@@ -207,28 +207,28 @@ FirstStage::getFetchingThread(FetchPriority &fetch_priority)
             return roundRobin();
 
           default:
-            return -1;
+            return InvalidThreadID;
         }
     } else {
-        int tid = *((*activeThreads).begin());
+        ThreadID tid = *activeThreads->begin();
 
         if (stageStatus[tid] == Running ||
             stageStatus[tid] == Idle) {
             return tid;
         } else {
-            return -1;
+            return InvalidThreadID;
         }
     }
 
 }
 
-int
+ThreadID
 FirstStage::roundRobin()
 {
-    list<unsigned>::iterator pri_iter = (*fetchPriorityList).begin();
-    list<unsigned>::iterator end      = (*fetchPriorityList).end();
+    list<ThreadID>::iterator pri_iter = fetchPriorityList->begin();
+    list<ThreadID>::iterator end      = fetchPriorityList->end();
 
-    int high_pri;
+    ThreadID high_pri;
 
     while (pri_iter != end) {
         high_pri = *pri_iter;
@@ -238,8 +238,8 @@ FirstStage::roundRobin()
         if (stageStatus[high_pri] == Running ||
             stageStatus[high_pri] == Idle) {
 
-            (*fetchPriorityList).erase(pri_iter);
-            (*fetchPriorityList).push_back(high_pri);
+            fetchPriorityList->erase(pri_iter);
+            fetchPriorityList->push_back(high_pri);
 
             return high_pri;
         }
@@ -247,5 +247,5 @@ FirstStage::roundRobin()
         pri_iter++;
     }
 
-    return -1;
+    return InvalidThreadID;
 }
diff --git a/src/cpu/inorder/first_stage.hh b/src/cpu/inorder/first_stage.hh
index 55914c85c..2a69678e4 100644
--- a/src/cpu/inorder/first_stage.hh
+++ b/src/cpu/inorder/first_stage.hh
@@ -56,10 +56,10 @@ class FirstStage : public PipelineStage {
     void processStage(bool &status_change);
 
     /** Process All Instructions Available */
-    void processInsts(unsigned tid);
+    void processInsts(ThreadID tid);
 
     /** Squash Instructions Above a Seq. Num */
-    void squash(InstSeqNum squash_seq_num, unsigned tid);
+    void squash(InstSeqNum squash_seq_num, ThreadID tid);
 
     /** There are no insts. coming from previous stages, so there is
      *	no need to sort insts here
@@ -69,7 +69,7 @@ class FirstStage : public PipelineStage {
     /** There are no skidBuffers for the first stage. So
      *  just use an empty function.
      */
-    void skidInsert(unsigned tid) { }
+    void skidInsert(ThreadID tid) { }
 
     /** The number of fetching threads in the CPU */
     int numFetchingThreads;
@@ -85,13 +85,13 @@ class FirstStage : public PipelineStage {
     FetchPriority fetchPolicy;
 
     /** List that has the threads organized by priority. */
-    std::list<unsigned> *fetchPriorityList;
+    std::list<ThreadID> *fetchPriorityList;
 
     /** Return the next fetching thread */
-    int getFetchingThread(FetchPriority &fetch_priority);
+    ThreadID getFetchingThread(FetchPriority &fetch_priority);
 
-    /** Return next thred given Round Robin Policy for Thread Fetching */
-    int roundRobin();
+    /** Return next thread given Round Robin Policy for Thread Fetching */
+    ThreadID roundRobin();
 };
 
 #endif // __CPU_INORDER_FIRST_STAGE_HH__
diff --git a/src/cpu/inorder/inorder_cpu_builder.cc b/src/cpu/inorder/inorder_cpu_builder.cc
index 0088a3bd9..5ee7b31db 100644
--- a/src/cpu/inorder/inorder_cpu_builder.cc
+++ b/src/cpu/inorder/inorder_cpu_builder.cc
@@ -42,7 +42,7 @@
 InOrderCPU *
 InOrderCPUParams::create()
 {
-    int actual_num_threads =
+    ThreadID actual_num_threads =
         (numThreads >= workload.size()) ? numThreads : workload.size();
 
     if (workload.size() == 0) {
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index ed63d9148..ee2e5500e 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -66,7 +66,7 @@ InOrderDynInst::InOrderDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
 InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
                                InOrderThreadState *state,
                                InstSeqNum seq_num,
-                               unsigned tid,
+                               ThreadID tid,
                                unsigned _asid)
     : traceData(NULL), cpu(cpu)
 {
@@ -385,7 +385,7 @@ InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
 
 /** Reads a integer register. */
 IntReg
-InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, unsigned tid)
+InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
 {
     DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
             threadNumber, seqNum, idx, instSrc[idx].integer);
@@ -479,7 +479,7 @@ InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
 }
 
 MiscReg
-InOrderDynInst::readRegOtherThread(unsigned reg_idx, int tid)
+InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
 {
     if (tid == -1) {
         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
@@ -553,9 +553,10 @@ InOrderDynInst::setMiscReg(int misc_reg, const MiscReg &val)
 }
 
 void
-InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val, int tid)
+InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
+                                  ThreadID tid)
 {
-    if (tid == -1) {
+    if (tid == InvalidThreadID) {
         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
     }
 
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 52465a712..031d882ee 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -112,8 +112,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
      *  @param cpu Pointer to the instruction's CPU.
      *  NOTE: Must set Binary Instrution through Member Function
      */
-    InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state, InstSeqNum seq_num,
-                   unsigned tid, unsigned asid = 0);
+    InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
+                   InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
 
     /** BaseDynInst constructor given a StaticInst pointer.
      *  @param _staticInst The StaticInst for this BaseDynInst.
@@ -347,7 +347,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     short readTid() { return threadNumber; }
 
     /** Sets the thread id. */
-    void setTid(unsigned tid) { threadNumber = tid; }
+    void setTid(ThreadID tid) { threadNumber = tid; }
 
     void setVpn(int id) { virtProcNumber = id; }
 
@@ -829,7 +829,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
      *  language (which is why the name isnt readIntSrc(...)) Note: That
      *  the source reg. value is set using the setSrcReg() function.
      */
-    IntReg readIntRegOperand(const StaticInst *si, int idx, unsigned tid=0);
+    IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
     FloatReg readFloatRegOperand(const StaticInst *si, int idx,
                           int width = TheISA::SingleWidth);
     TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
@@ -881,8 +881,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
     void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val);
 
-    virtual uint64_t readRegOtherThread(unsigned idx, int tid = -1);
-    virtual void setRegOtherThread(unsigned idx, const uint64_t &val, int tid = -1);
+    virtual uint64_t readRegOtherThread(unsigned idx,
+                                        ThreadID tid = InvalidThreadID);
+    virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
+                                   ThreadID tid = InvalidThreadID);
 
     /** Sets the number of consecutive store conditional failures. */
     void setStCondFailures(unsigned sc_failures)
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index dd31716eb..46b1cbad0 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -49,7 +49,7 @@ PipelineStage::PipelineStage(Params *params, unsigned stage_num)
 void
 PipelineStage::init(Params *params)
 {
-    for(int tid=0; tid < numThreads; tid++) {
+    for(ThreadID tid = 0; tid < numThreads; tid++) {
         stageStatus[tid] = Idle;
 
         for (int stNum = 0; stNum < NumStages; stNum++) {
@@ -162,7 +162,7 @@ PipelineStage::setNextStageQueue(TimeBuffer<InterStageStruct> *next_stage_ptr)
 
 
 void
-PipelineStage::setActiveThreads(list<unsigned> *at_ptr)
+PipelineStage::setActiveThreads(list<ThreadID> *at_ptr)
 {
     DPRINTF(InOrderStage, "Setting active threads list pointer.\n");
     activeThreads = at_ptr;
@@ -194,20 +194,20 @@ PipelineStage::takeOverFrom()
     _status = Inactive;
 
     // Be sure to reset state and clear out any old instructions.
-    for (int i = 0; i < numThreads; ++i) {
-        stageStatus[i] = Idle;
+    for (ThreadID tid = 0; tid < numThreads; ++tid) {
+        stageStatus[tid] = Idle;
 
         for (int stNum = 0; stNum < NumStages; stNum++) {
-            stalls[i].stage[stNum] = false;
+            stalls[tid].stage[stNum] = false;
         }
 
-        stalls[i].resources.clear();
+        stalls[tid].resources.clear();
 
-        while (!insts[i].empty())
-            insts[i].pop();
+        while (!insts[tid].empty())
+            insts[tid].pop();
 
-        while (!skidBuffer[i].empty())
-            skidBuffer[i].pop();
+        while (!skidBuffer[tid].empty())
+            skidBuffer[tid].pop();
     }
     wroteToTimeBuffer = false;
 }
@@ -215,7 +215,7 @@ PipelineStage::takeOverFrom()
 
 
 bool
-PipelineStage::checkStall(unsigned tid) const
+PipelineStage::checkStall(ThreadID tid) const
 {
     bool ret_val = false;
 
@@ -243,7 +243,7 @@ PipelineStage::checkStall(unsigned tid) const
 
 
 void
-PipelineStage::removeStalls(unsigned tid)
+PipelineStage::removeStalls(ThreadID tid)
 {
     for (int stNum = 0; stNum < NumStages; stNum++) {
         stalls[tid].stage[stNum] = false;
@@ -258,13 +258,13 @@ PipelineStage::prevStageInstsValid()
 }
 
 bool
-PipelineStage::isBlocked(unsigned tid)
+PipelineStage::isBlocked(ThreadID tid)
 {
     return stageStatus[tid] == Blocked;
 }
 
 bool
-PipelineStage::block(unsigned tid)
+PipelineStage::block(ThreadID tid)
 {
     DPRINTF(InOrderStage, "[tid:%d]: Blocking, sending block signal back to previous stages.\n", tid);
 
@@ -293,7 +293,7 @@ PipelineStage::block(unsigned tid)
 }
 
 void
-PipelineStage::blockDueToBuffer(unsigned tid)
+PipelineStage::blockDueToBuffer(ThreadID tid)
 {
     DPRINTF(InOrderStage, "[tid:%d]: Blocking instructions from passing to next stage.\n", tid);
 
@@ -308,7 +308,7 @@ PipelineStage::blockDueToBuffer(unsigned tid)
 }
 
 bool
-PipelineStage::unblock(unsigned tid)
+PipelineStage::unblock(ThreadID tid)
 {
     // Stage is done unblocking only if the skid buffer is empty.
     if (skidBuffer[tid].empty()) {
@@ -329,7 +329,7 @@ PipelineStage::unblock(unsigned tid)
 }
 
 void
-PipelineStage::squashDueToBranch(DynInstPtr &inst, unsigned tid)
+PipelineStage::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
 {
     if (cpu->squashSeqNum[tid] < inst->seqNum &&
         cpu->lastSquashCycle[tid] == curTick){
@@ -367,8 +367,7 @@ PipelineStage::squashDueToBranch(DynInstPtr &inst, unsigned tid)
 }
 
 void
-PipelineStage::squashPrevStageInsts(InstSeqNum squash_seq_num,
-                                    unsigned tid)
+PipelineStage::squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid)
 {
     DPRINTF(InOrderStage, "[tid:%i]: Removing instructions from "
             "incoming stage queue.\n", tid);
@@ -387,7 +386,7 @@ PipelineStage::squashPrevStageInsts(InstSeqNum squash_seq_num,
 }
 
 void
-PipelineStage::squash(InstSeqNum squash_seq_num, unsigned tid)
+PipelineStage::squash(InstSeqNum squash_seq_num, ThreadID tid)
 {
     // Set status to squashing.
     stageStatus[tid] = Squashing;
@@ -450,7 +449,7 @@ PipelineStage::canSendInstToStage(unsigned stage_num)
 }
 
 void
-PipelineStage::skidInsert(unsigned tid)
+PipelineStage::skidInsert(ThreadID tid)
 {
     DynInstPtr inst = NULL;
 
@@ -484,9 +483,9 @@ PipelineStage::skidSize()
 bool
 PipelineStage::skidsEmpty()
 {
-    list<unsigned>::iterator threads = (*activeThreads).begin();
+    list<ThreadID>::iterator threads = activeThreads->begin();
 
-    while (threads != (*activeThreads).end()) {
+    while (threads != activeThreads->end()) {
         if (!skidBuffer[*threads++].empty())
             return false;
     }
@@ -501,12 +500,10 @@ PipelineStage::updateStatus()
 {
     bool any_unblocking = false;
 
-    list<unsigned>::iterator threads = (*activeThreads).begin();
-
-    threads = (*activeThreads).begin();
+    list<ThreadID>::iterator threads = activeThreads->begin();
 
-    while (threads != (*activeThreads).end()) {
-        unsigned tid = *threads++;
+    while (threads != activeThreads->end()) {
+        ThreadID tid = *threads++;
 
         if (stageStatus[tid] == Unblocking) {
             any_unblocking = true;
@@ -561,7 +558,7 @@ PipelineStage::sortInsts()
                     prevStage->insts[i]->readTid(),
                     prevStage->insts[i]->seqNum);
 
-            int tid = prevStage->insts[i]->threadNumber;
+            ThreadID tid = prevStage->insts[i]->threadNumber;
 
             DynInstPtr inst = prevStage->insts[i];
 
@@ -576,7 +573,7 @@ PipelineStage::sortInsts()
 
 
 void
-PipelineStage::readStallSignals(unsigned tid)
+PipelineStage::readStallSignals(ThreadID tid)
 {
     for (int stage_idx = stageNum+1; stage_idx <= lastStallingStage[tid];
          stage_idx++) {
@@ -597,7 +594,7 @@ PipelineStage::readStallSignals(unsigned tid)
 
 
 bool
-PipelineStage::checkSignalsAndUpdate(unsigned tid)
+PipelineStage::checkSignalsAndUpdate(ThreadID tid)
 {
     // Check if there's a squash signal, squash if there is.
     // Check stall signals, block if necessary.
@@ -691,14 +688,14 @@ PipelineStage::tick()
 }
 
 void
-PipelineStage::setResStall(ResReqPtr res_req, unsigned tid)
+PipelineStage::setResStall(ResReqPtr res_req, ThreadID tid)
 {
     DPRINTF(InOrderStage, "Inserting stall from %s.\n", res_req->res->name());
     stalls[tid].resources.push_back(res_req);
 }
 
 void
-PipelineStage::unsetResStall(ResReqPtr res_req, unsigned tid)
+PipelineStage::unsetResStall(ResReqPtr res_req, ThreadID tid)
 {
     // Search through stalls to find stalling request and then
     // remove it
@@ -731,11 +728,11 @@ PipelineStage::unsetResStall(ResReqPtr res_req, unsigned tid)
 void
 PipelineStage::processStage(bool &status_change)
 {
-    list<unsigned>::iterator threads = (*activeThreads).begin();
+    list<ThreadID>::iterator threads = activeThreads->begin();
 
     //Check stall and squash signals.
-    while (threads != (*activeThreads).end()) {
-        unsigned tid = *threads++;
+    while (threads != activeThreads->end()) {
+        ThreadID tid = *threads++;
 
         DPRINTF(InOrderStage,"Processing [tid:%i]\n",tid);
         status_change =  checkSignalsAndUpdate(tid) || status_change;
@@ -756,7 +753,7 @@ PipelineStage::processStage(bool &status_change)
 }
 
 void
-PipelineStage::processThread(bool &status_change, unsigned tid)
+PipelineStage::processThread(bool &status_change, ThreadID tid)
 {
     // If status is Running or idle,
     //     call stageInsts()
@@ -801,7 +798,7 @@ PipelineStage::processThread(bool &status_change, unsigned tid)
 
 
 void
-PipelineStage::processInsts(unsigned tid)
+PipelineStage::processInsts(ThreadID tid)
 {
     // Instructions can come either from the skid buffer or the list of
     // instructions coming from fetch, depending on stage's status.
@@ -888,9 +885,9 @@ bool
 PipelineStage::processInstSchedule(DynInstPtr inst)
 {
     bool last_req_completed = true;
-    int tid;
-
-    tid = inst->readTid();
+#if TRACING_ON
+    ThreadID tid = inst->readTid();
+#endif
 
     if (inst->nextResStage() == stageNum) {
         int res_stage_num = inst->nextResStage();
@@ -951,7 +948,7 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
         inst->nextStage++;
 
     bool success = false;
-    int tid = inst->readTid();
+    ThreadID tid = inst->readTid();
     int next_stage = inst->nextStage;
     int prev_stage = next_stage - 1;
 
@@ -1012,8 +1009,7 @@ PipelineStage::dumpInsts()
 {
     cprintf("Insts in Stage %i skidbuffers\n",stageNum);
 
-    for (int tid=0; tid < ThePipeline::MaxThreads; tid++) {
-
+    for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
         std::queue<DynInstPtr> copy_buff(skidBuffer[tid]);
 
         while (!copy_buff.empty()) {
diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh
index b074639fb..86ee98132 100644
--- a/src/cpu/inorder/pipeline_stage.hh
+++ b/src/cpu/inorder/pipeline_stage.hh
@@ -80,7 +80,7 @@ class PipelineStage
     unsigned stageWidth;
 
     /** Number of Threads*/
-    unsigned numThreads;
+    ThreadID numThreads;
 
     /** Stage status. */
     StageStatus _status;
@@ -108,7 +108,7 @@ class PipelineStage
     /** Sets CPU pointer. */
     virtual void setCPU(InOrderCPU *cpu_ptr);
 
-    virtual void scheduleStageStart(int delay, int tid) { }
+    virtual void scheduleStageStart(int delay, ThreadID tid) { }
 
     /** Sets the main backwards communication time buffer pointer. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
@@ -120,11 +120,11 @@ class PipelineStage
     void setNextStageQueue(TimeBuffer<InterStageStruct> *next_stage_ptr);
 
     /** Sets pointer to list of active threads. */
-    void setActiveThreads(std::list<unsigned> *at_ptr);
+    void setActiveThreads(std::list<ThreadID> *at_ptr);
 
     bool nextStageQueueValid(int stage_num);
 
-    bool isBlocked(unsigned tid);
+    bool isBlocked(ThreadID tid);
 
     /** Changes the status of this stage to active, and indicates this
      * to the CPU.
@@ -148,13 +148,13 @@ class PipelineStage
     virtual void tick();
 
     /** Set a resource stall in the pipeline-stage */
-    void setResStall(ResReqPtr res_req, unsigned tid);
+    void setResStall(ResReqPtr res_req, ThreadID tid);
 
     /** Unset a resource stall in the pipeline-stage */
-    void unsetResStall(ResReqPtr res_req, unsigned tid);
+    void unsetResStall(ResReqPtr res_req, ThreadID tid);
 
     /** Remove all stall signals for a particular thread; */
-    virtual void removeStalls(unsigned tid);
+    virtual void removeStalls(ThreadID tid);
 
     /** Is there room in the stage buffer? */
     int stageBufferAvail();
@@ -168,14 +168,14 @@ class PipelineStage
      * change (ie switching from from blocking to unblocking).
      * @param tid Thread id to stage instructions from.
      */
-    virtual void processThread(bool &status_change, unsigned tid);
+    virtual void processThread(bool &status_change, ThreadID tid);
 
     /** Processes instructions from fetch and passes them on to rename.
      * Decoding of instructions actually happens when they are created in
      * fetch, so this function mostly checks if PC-relative branches are
      * correct.
      */
-    virtual void processInsts(unsigned tid);
+    virtual void processInsts(ThreadID tid);
 
     /** Process all resources on an instruction's resource schedule */
     virtual bool processInstSchedule(DynInstPtr inst);
@@ -189,7 +189,7 @@ class PipelineStage
     /** Inserts a thread's instructions into the skid buffer, to be staged
      * once stage unblocks.
      */
-    virtual void skidInsert(unsigned tid);
+    virtual void skidInsert(ThreadID tid);
 
     /** Total size of all skid buffers */
     int skidSize();
@@ -206,13 +206,13 @@ class PipelineStage
     void sortInsts();
 
     /** Reads all stall signals from the backwards communication timebuffer. */
-    virtual void readStallSignals(unsigned tid);
+    virtual void readStallSignals(ThreadID tid);
 
     /** Checks all input signals and updates stage's status appropriately. */
-    virtual bool checkSignalsAndUpdate(unsigned tid);
+    virtual bool checkSignalsAndUpdate(ThreadID tid);
 
     /** Checks all stall signals, and returns if any are true. */
-    virtual bool checkStall(unsigned tid) const;
+    virtual bool checkStall(ThreadID tid) const;
 
     /** Returns if there any instructions from the previous stage
      * on this cycle.
@@ -223,30 +223,30 @@ class PipelineStage
      * become blocked.
      * @return Returns true if there is a status change.
      */
-    virtual bool block(unsigned tid);
+    virtual bool block(ThreadID tid);
 
-    void blockDueToBuffer(unsigned tid);
+    void blockDueToBuffer(ThreadID tid);
 
     /** Switches stage to unblocking if the skid buffer is empty, and
      * signals back that stage has unblocked.
      * @return Returns true if there is a status change.
      */
-    virtual bool unblock(unsigned tid);
+    virtual bool unblock(ThreadID tid);
 
 
   public:
     /** Squashes if there is a PC-relative branch that was predicted
      * incorrectly. Sends squash information back to fetch.
      */
-    virtual void squashDueToBranch(DynInstPtr &inst, unsigned tid);
+    virtual void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
 
     /** Squash instructions from stage buffer  */
-    virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, unsigned tid);
+    virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid);
 
     /** Squashes due to commit signalling a squash. Changes status to
      *  squashing and clears block/unblock signals as needed.
      */
-    virtual void squash(InstSeqNum squash_num, unsigned tid);
+    virtual void squash(InstSeqNum squash_num, ThreadID tid);
 
     void dumpInsts();
 
@@ -257,7 +257,7 @@ class PipelineStage
     Trace::InOrderTrace *tracer;
 
     /** List of active thread ids */
-    std::list<unsigned> *activeThreads;
+    std::list<ThreadID> *activeThreads;
 
     /** Queue of all instructions coming from previous stage on this cycle. */
     std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/resource.cc b/src/cpu/inorder/resource.cc
index 49afefd98..cb5681bc1 100644
--- a/src/cpu/inorder/resource.cc
+++ b/src/cpu/inorder/resource.cc
@@ -283,7 +283,7 @@ Resource::execute(int slot_idx)
 }
 
 void
-Resource::deactivateThread(unsigned tid)
+Resource::deactivateThread(ThreadID tid)
 {
     // In the most basic case, deactivation means squashing everything
     // from a particular thread
@@ -292,7 +292,8 @@ Resource::deactivateThread(unsigned tid)
 }
 
 void
-Resource::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
+Resource::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+                 ThreadID tid)
 {
     std::vector<int> slot_remove_list;
 
diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index 5b4977158..7935e5517 100644
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -84,17 +84,17 @@ class Resource {
     virtual void regStats();
 
     /** Resources that care about thread activation override this. */
-    virtual void activateThread(unsigned tid) { }
+    virtual void activateThread(ThreadID tid) { }
 
     /** Deactivate Thread. Default action is to squash all instructions
      *  from deactivated thread.
      */
-    virtual void deactivateThread(unsigned tid);
+    virtual void deactivateThread(ThreadID tid);
 
     /** Resources that care when an instruction has been graduated
      *  can override this
      */
-    virtual void instGraduated(InstSeqNum seq_num,unsigned tid) { }
+    virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
 
     /** Request usage of this resource. Returns a ResourceRequest object
      *  with all the necessary resource information
@@ -151,7 +151,8 @@ class Resource {
     { panic("writeHint undefined for %s", name()); }
 
     /** Squash All Requests After This Seq Num */
-    virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
+    virtual void squash(DynInstPtr inst, int stage_num,
+                        InstSeqNum squash_seq_num, ThreadID tid);
 
     /** The number of instructions available that this resource can
      *  can still process
@@ -347,8 +348,8 @@ class ResourceRequest
     int getStageNum() { return stageNum; }
 
     /** Set/Get Thread Ids */
-    void setTid(unsigned _tid) { tid = _tid; }
-    int getTid() { return tid; }
+    void setTid(ThreadID _tid) { tid = _tid; }
+    ThreadID getTid() { return tid; }
 
     /** Instruction this request is for */
     DynInstPtr getInst() { return inst; }
@@ -393,7 +394,7 @@ class ResourceRequest
 
   protected:
     /** Resource Identification */
-    int tid;
+    ThreadID tid;
     int stageNum;
     int resIdx;
     int slotNum;
diff --git a/src/cpu/inorder/resource_pool.9stage.cc b/src/cpu/inorder/resource_pool.9stage.cc
index 4a0258e71..05ce91faa 100644
--- a/src/cpu/inorder/resource_pool.9stage.cc
+++ b/src/cpu/inorder/resource_pool.9stage.cc
@@ -146,7 +146,8 @@ ResourcePool::request(int res_idx, DynInstPtr inst)
 }
 
 void
-ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num, int tid)
+ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
+                     ThreadID tid)
 {
     resources[res_idx]->squash(inst, ThePipeline::NumStages-1, done_seq_num, tid);
 }
@@ -165,7 +166,7 @@ ResourcePool::slotsInUse(int res_idx)
 
 void
 ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
-                            int delay,  int res_idx, int tid)
+                            int delay,  int res_idx, ThreadID tid)
 {
     assert(delay >= 0);
 
@@ -246,7 +247,8 @@ ResourcePool::unscheduleEvent(int res_idx, DynInstPtr inst)
 }
 
 void
-ResourcePool::squashAll(DynInstPtr inst, int stage_num, InstSeqNum done_seq_num, unsigned tid)
+ResourcePool::squashAll(DynInstPtr inst, int stage_num,
+                        InstSeqNum done_seq_num, ThreadID tid)
 {
     DPRINTF(Resource, "[tid:%i] Stage %i squashing all instructions above [sn:%i].\n",
             stage_num, tid, done_seq_num);
@@ -259,7 +261,7 @@ ResourcePool::squashAll(DynInstPtr inst, int stage_num, InstSeqNum done_seq_num,
 }
 
 void
-ResourcePool::activateAll(unsigned tid)
+ResourcePool::activateAll(ThreadID tid)
 {
     DPRINTF(Resource, "[tid:%i] Broadcasting Thread Activation to all resources.\n",
             tid);
@@ -272,7 +274,7 @@ ResourcePool::activateAll(unsigned tid)
 }
 
 void
-ResourcePool::deactivateAll(unsigned tid)
+ResourcePool::deactivateAll(ThreadID tid)
 {
     DPRINTF(Resource, "[tid:%i] Broadcasting Thread Deactivation to all resources.\n",
             tid);
@@ -285,7 +287,7 @@ ResourcePool::deactivateAll(unsigned tid)
 }
 
 void
-ResourcePool::instGraduated(InstSeqNum seq_num,unsigned tid)
+ResourcePool::instGraduated(InstSeqNum seq_num, ThreadID tid)
 {
     DPRINTF(Resource, "[tid:%i] Broadcasting [sn:%i] graduation to all resources.\n",
             tid, seq_num);
diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc
index 7bcf2585b..0d78c232b 100644
--- a/src/cpu/inorder/resource_pool.cc
+++ b/src/cpu/inorder/resource_pool.cc
@@ -164,7 +164,8 @@ ResourcePool::request(int res_idx, DynInstPtr inst)
 }
 
 void
-ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num, int tid)
+ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
+                     ThreadID tid)
 {
     resources[res_idx]->squash(inst, ThePipeline::NumStages-1, done_seq_num, tid);
 }
@@ -183,7 +184,7 @@ ResourcePool::slotsInUse(int res_idx)
 
 void
 ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
-                            int delay,  int res_idx, int tid)
+                            int delay,  int res_idx, ThreadID tid)
 {
     assert(delay >= 0);
 
@@ -261,7 +262,8 @@ ResourcePool::unscheduleEvent(int res_idx, DynInstPtr inst)
 }
 
 void
-ResourcePool::squashAll(DynInstPtr inst, int stage_num, InstSeqNum done_seq_num, unsigned tid)
+ResourcePool::squashAll(DynInstPtr inst, int stage_num,
+                        InstSeqNum done_seq_num, ThreadID tid)
 {
     DPRINTF(Resource, "[tid:%i] Stage %i squashing all instructions above [sn:%i].\n",
             stage_num, tid, done_seq_num);
@@ -274,7 +276,7 @@ ResourcePool::squashAll(DynInstPtr inst, int stage_num, InstSeqNum done_seq_num,
 }
 
 void
-ResourcePool::activateAll(unsigned tid)
+ResourcePool::activateAll(ThreadID tid)
 {
     DPRINTF(Resource, "[tid:%i] Broadcasting Thread Activation to all resources.\n",
             tid);
@@ -287,7 +289,7 @@ ResourcePool::activateAll(unsigned tid)
 }
 
 void
-ResourcePool::deactivateAll(unsigned tid)
+ResourcePool::deactivateAll(ThreadID tid)
 {
     DPRINTF(Resource, "[tid:%i] Broadcasting Thread Deactivation to all resources.\n",
             tid);
@@ -300,7 +302,7 @@ ResourcePool::deactivateAll(unsigned tid)
 }
 
 void
-ResourcePool::instGraduated(InstSeqNum seq_num,unsigned tid)
+ResourcePool::instGraduated(InstSeqNum seq_num, ThreadID tid)
 {
     DPRINTF(Resource, "[tid:%i] Broadcasting [sn:%i] graduation to all resources.\n",
             tid, seq_num);
@@ -322,7 +324,7 @@ ResourcePool::ResPoolEvent::ResPoolEvent(ResourcePool *_resPool,
                                          DynInstPtr _inst,
                                          int stage_num,
                                          InstSeqNum seq_num,
-                                         unsigned _tid)
+                                         ThreadID _tid)
     : Event(CPU_Tick_Pri), resPool(_resPool),
       eventType(e_type), inst(_inst), seqNum(seq_num),
       stageNum(stage_num), tid(_tid)
diff --git a/src/cpu/inorder/resource_pool.hh b/src/cpu/inorder/resource_pool.hh
index 42a07390c..016fae2bf 100644
--- a/src/cpu/inorder/resource_pool.hh
+++ b/src/cpu/inorder/resource_pool.hh
@@ -81,7 +81,7 @@ class ResourcePool {
 
         int stageNum;
 
-        unsigned tid;
+        ThreadID tid;
 
       public:
         /** Constructs a resource event. */
@@ -93,14 +93,14 @@ class ResourcePool {
                      DynInstPtr _inst,
                      int stage_num,
                      InstSeqNum seq_num,
-                     unsigned _tid);
+                     ThreadID _tid);
 
         /** Set Type of Event To Be Scheduled */
         void setEvent(InOrderCPU::CPUEventType e_type,
                       DynInstPtr _inst,
                       int stage_num,
                       InstSeqNum seq_num,
-                      unsigned _tid)
+                      ThreadID _tid)
         {
             eventType = e_type;
             inst = _inst;
@@ -153,20 +153,21 @@ class ResourcePool {
     ResReqPtr request(int res_idx, DynInstPtr inst);
 
     /** Squash The Resource */
-    void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num, int tid);
+    void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
+                ThreadID tid);
 
     /** Squash All Resources in Pool after Done Seq. Num */
     void squashAll(DynInstPtr inst, int stage_num,
-                   InstSeqNum done_seq_num, unsigned tid);
+                   InstSeqNum done_seq_num, ThreadID tid);
 
     /** Activate Thread in all resources */
-    void activateAll(unsigned tid);
+    void activateAll(ThreadID tid);
 
     /** De-Activate Thread in all resources */
-    void deactivateAll(unsigned tid);
+    void deactivateAll(ThreadID tid);
 
     /** Broadcast graduation to all resources */
-    void instGraduated(InstSeqNum seq_num,unsigned tid);
+    void instGraduated(InstSeqNum seq_num, ThreadID tid);
 
     /** The number of instructions available that a resource can
      *  can still process.
@@ -178,7 +179,7 @@ class ResourcePool {
 
     /** Schedule resource event, regardless of its current state. */
     void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
-                       int delay = 0, int res_idx = 0, int tid = 0);
+                       int delay = 0, int res_idx = 0, ThreadID tid = 0);
 
    /** UnSchedule resource event, regardless of its current state. */
     void unscheduleEvent(int res_idx, DynInstPtr inst);
diff --git a/src/cpu/inorder/resources/agen_unit.cc b/src/cpu/inorder/resources/agen_unit.cc
index 44cd002ef..44bf8c0ad 100644
--- a/src/cpu/inorder/resources/agen_unit.cc
+++ b/src/cpu/inorder/resources/agen_unit.cc
@@ -42,10 +42,11 @@ AGENUnit::execute(int slot_num)
     ResourceRequest* agen_req = reqMap[slot_num];
     DynInstPtr inst = reqMap[slot_num]->inst;
     Fault fault = reqMap[slot_num]->fault;
-    int tid;
+#if TRACING_ON
+    ThreadID tid = inst->readTid();
+#endif
     int seq_num = inst->seqNum;
 
-    tid = inst->readTid();
     agen_req->fault = NoFault;
 
     switch (agen_req->cmd)
@@ -54,22 +55,27 @@ AGENUnit::execute(int slot_num)
         {
             // Load/Store Instruction
             if (inst->isMemRef()) {
-                DPRINTF(InOrderAGEN, "[tid:%i] Generating Address for [sn:%i] (%s).\n",
-                        tid, inst->seqNum, inst->staticInst->getName());
+                DPRINTF(InOrderAGEN,
+                        "[tid:%i] Generating Address for [sn:%i] (%s).\n",
+                        tid, seq_num, inst->staticInst->getName());
 
                 fault = inst->calcEA();
                 inst->setMemAddr(inst->getEA());
 
-                DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective address calculated to be: "
-                        "%#x.\n", tid, inst->seqNum, inst->getEA());
+                DPRINTF(InOrderAGEN,
+                    "[tid:%i] [sn:%i] Effective address calculated as: %#x\n",
+                    tid, seq_num, inst->getEA());
 
                 if (fault == NoFault) {
                     agen_req->done();
                 } else {
-                    fatal("%s encountered while calculating address for [sn:%i]",fault->name(), seq_num);
+                    fatal("%s encountered while calculating address [sn:%i]",
+                          fault->name(), seq_num);
                 }
             } else {
-                DPRINTF(InOrderAGEN, "[tid:] Ignoring non-memory instruction [sn:%i].\n", tid, seq_num);
+                DPRINTF(InOrderAGEN,
+                        "[tid:] Ignoring non-memory instruction [sn:%i]\n",
+                        tid, seq_num);
                 agen_req->done();
             }
         }
diff --git a/src/cpu/inorder/resources/bpred_unit.cc b/src/cpu/inorder/resources/bpred_unit.cc
index df6b33792..2ed8586aa 100644
--- a/src/cpu/inorder/resources/bpred_unit.cc
+++ b/src/cpu/inorder/resources/bpred_unit.cc
@@ -142,7 +142,7 @@ BPredUnit::takeOverFrom()
 
 
 bool
-BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
+BPredUnit::predict(DynInstPtr &inst, Addr &PC, ThreadID tid)
 {
     // See if branch predictor predicts taken.
     // If so, get its target addr either from the BTB or the RAS.
@@ -268,7 +268,7 @@ BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
 
 
 void
-BPredUnit::update(const InstSeqNum &done_sn, unsigned tid)
+BPredUnit::update(const InstSeqNum &done_sn, ThreadID tid)
 {
     DPRINTF(Resource, "BranchPred: [tid:%i]: Commiting branches until sequence"
             "number %lli.\n", tid, done_sn);
@@ -286,7 +286,7 @@ BPredUnit::update(const InstSeqNum &done_sn, unsigned tid)
 
 
 void
-BPredUnit::squash(const InstSeqNum &squashed_sn, unsigned tid)
+BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid)
 {
     History &pred_hist = predHist[tid];
 
@@ -321,8 +321,8 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, unsigned tid)
 void
 BPredUnit::squash(const InstSeqNum &squashed_sn,
                         const Addr &corr_target,
-                        const bool actually_taken,
-                        unsigned tid)
+                        bool actually_taken,
+                        ThreadID tid)
 {
     // Now that we know that a branch was mispredicted, we need to undo
     // all the branches that have been seen up until this branch and
diff --git a/src/cpu/inorder/resources/bpred_unit.hh b/src/cpu/inorder/resources/bpred_unit.hh
index bd68459d1..abbb70e0d 100644
--- a/src/cpu/inorder/resources/bpred_unit.hh
+++ b/src/cpu/inorder/resources/bpred_unit.hh
@@ -87,7 +87,7 @@ class BPredUnit
      * @param tid The thread id.
      * @return Returns if the branch is taken or not.
      */
-    bool predict(ThePipeline::DynInstPtr &inst, Addr &PC, unsigned tid);
+    bool predict(ThePipeline::DynInstPtr &inst, Addr &PC, ThreadID tid);
 
     // @todo: Rename this function.
     void BPUncond(void * &bp_history);
@@ -98,7 +98,7 @@ class BPredUnit
      * @param done_sn The sequence number to commit any older updates up until.
      * @param tid The thread id.
      */
-    void update(const InstSeqNum &done_sn, unsigned tid);
+    void update(const InstSeqNum &done_sn, ThreadID tid);
 
     /**
      * Squashes all outstanding updates until a given sequence number.
@@ -106,7 +106,7 @@ class BPredUnit
      * until.
      * @param tid The thread id.
      */
-    void squash(const InstSeqNum &squashed_sn, unsigned tid);
+    void squash(const InstSeqNum &squashed_sn, ThreadID tid);
 
     /**
      * Squashes all outstanding updates until a given sequence number, and
@@ -118,7 +118,7 @@ class BPredUnit
      * @param tid The thread id.
      */
     void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
-                bool actually_taken, unsigned tid);
+                bool actually_taken, ThreadID tid);
 
     /**
      * @param bp_history Pointer to the history object.  The predictor
@@ -178,8 +178,8 @@ class BPredUnit
          * information needed to update the predictor, BTB, and RAS.
          */
         PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
-                         const bool pred_taken, void *bp_history,
-                         const unsigned _tid)
+                         bool pred_taken, void *bp_history,
+                         ThreadID _tid)
             : seqNum(seq_num), PC(inst_PC), RASTarget(0),
               RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
               wasCall(0), bpHistory(bp_history)
@@ -198,7 +198,7 @@ class BPredUnit
         unsigned RASIndex;
 
         /** The thread id. */
-        unsigned tid;
+        ThreadID tid;
 
         /** Whether or not it was predicted taken. */
         bool predTaken;
diff --git a/src/cpu/inorder/resources/branch_predictor.cc b/src/cpu/inorder/resources/branch_predictor.cc
index d8c0730af..905de0794 100644
--- a/src/cpu/inorder/resources/branch_predictor.cc
+++ b/src/cpu/inorder/resources/branch_predictor.cc
@@ -65,7 +65,7 @@ BranchPredictor::execute(int slot_num)
     ResourceRequest* bpred_req = reqMap[slot_num];
 
     DynInstPtr inst = bpred_req->inst;
-    int tid = inst->readTid();
+    ThreadID tid = inst->readTid();
     int seq_num = inst->seqNum;
     //int stage_num = bpred_req->getStageNum();
 
@@ -136,14 +136,14 @@ BranchPredictor::execute(int slot_num)
 
 void
 BranchPredictor::squash(DynInstPtr inst, int squash_stage,
-                        InstSeqNum squash_seq_num, unsigned tid)
+                        InstSeqNum squash_seq_num, ThreadID tid)
 {
     DPRINTF(InOrderBPred, "Squashing...\n");
     branchPred.squash(squash_seq_num, tid);
 }
 
 void
-BranchPredictor::instGraduated(InstSeqNum seq_num,unsigned tid)
+BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid)
 {
     branchPred.update(seq_num, tid);
 }
diff --git a/src/cpu/inorder/resources/branch_predictor.hh b/src/cpu/inorder/resources/branch_predictor.hh
index 47053910d..7d0b3348a 100644
--- a/src/cpu/inorder/resources/branch_predictor.hh
+++ b/src/cpu/inorder/resources/branch_predictor.hh
@@ -61,9 +61,9 @@ class BranchPredictor : public Resource {
     virtual void execute(int slot_num);
 
     virtual void squash(DynInstPtr inst, int stage_num,
-                        InstSeqNum squash_seq_num, unsigned tid);
+                        InstSeqNum squash_seq_num, ThreadID tid);
 
-    virtual void instGraduated(InstSeqNum seq_num,unsigned tid);
+    virtual void instGraduated(InstSeqNum seq_num, ThreadID tid);
 
   protected:
     /** List of instructions this resource is currently
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 5d5d4d45d..5677810f6 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -258,17 +258,10 @@ Fault
 CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
                        int flags, TheISA::TLB::Mode tlb_mode)
 {
-    int tid;
-    int seq_num;
-    Addr aligned_addr;
-    unsigned stage_num;
-    unsigned slot_idx;
-
-    tid = inst->readTid();
-    seq_num = inst->seqNum;
-    aligned_addr = inst->getMemAddr();
-    stage_num = cache_req->getStageNum();
-    slot_idx = cache_req->getSlot();
+    ThreadID tid = inst->readTid();
+    Addr aligned_addr = inst->getMemAddr();
+    unsigned stage_num = cache_req->getStageNum();
+    unsigned slot_idx = cache_req->getSlot();
 
     if (tlb_mode == TheISA::TLB::Execute) {
             inst->fetchMemReq = new Request(inst->readTid(), aligned_addr,
@@ -290,7 +283,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
     if (cache_req->fault != NoFault) {
         DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
                 "addr:%08p for [sn:%i].\n", tid, cache_req->fault->name(),
-                cache_req->memReq->getVaddr(), seq_num);
+                cache_req->memReq->getVaddr(), inst->seqNum);
 
         cpu->pipelineStage[stage_num]->setResStall(cache_req, tid);
 
@@ -303,7 +296,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
         cpu->trap(cache_req->fault, tid);
     } else {
         DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
-                "to phys. addr:%08p.\n", tid, seq_num,
+                "to phys. addr:%08p.\n", tid, inst->seqNum,
                 cache_req->memReq->getVaddr(),
                 cache_req->memReq->getPaddr());
     }
@@ -361,11 +354,11 @@ CacheUnit::execute(int slot_num)
     assert(cache_req);
 
     DynInstPtr inst = cache_req->inst;
-    int tid;
-    int seq_num;
+#if TRACING_ON
+    ThreadID tid = inst->readTid();
+    int seq_num = inst->seqNum;
+#endif
 
-    tid = inst->readTid();
-    seq_num = inst->seqNum;
     cache_req->fault = NoFault;
 
     switch (cache_req->cmd)
@@ -381,8 +374,8 @@ CacheUnit::execute(int slot_num)
             if (cache_req->fault == NoFault) {
 
                 DPRINTF(InOrderCachePort,
-                        "[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
-                        tid, name(), cache_req->inst->getMemAddr());
+                    "[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
+                    tid, name(), cache_req->inst->getMemAddr());
 
                 cache_req->reqData = new uint8_t[acc_size];
 
@@ -499,9 +492,9 @@ Fault
 CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res)
 {
     Fault fault = NoFault;
-    int tid = 0;
-
-    tid = inst->readTid();
+#if TRACING_ON
+    ThreadID tid = inst->readTid();
+#endif
 
     CacheReqPtr cache_req
         = dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
@@ -627,10 +620,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
     // Get resource request info
     unsigned stage_num = cache_req->getStageNum();
     DynInstPtr inst = cache_req->inst;
-    unsigned tid;
-
-
-    tid = cache_req->inst->readTid();
+    ThreadID tid = cache_req->inst->readTid();
 
     if (!cache_req->isSquashed()) {
         if (inst->resSched.top()->cmd == CompleteFetch) {
@@ -752,7 +742,7 @@ CacheUnitEvent::process()
 {
     DynInstPtr inst = resource->reqMap[slotIdx]->inst;
     int stage_num = resource->reqMap[slotIdx]->getStageNum();
-    int tid = inst->threadNumber;
+    ThreadID tid = inst->threadNumber;
     CacheReqPtr req_ptr = dynamic_cast<CacheReqPtr>(resource->reqMap[slotIdx]);
 
     DPRINTF(InOrderTLB, "Waking up from TLB Miss caused by [sn:%i].\n",
@@ -774,7 +764,7 @@ CacheUnitEvent::process()
 
 void
 CacheUnit::squash(DynInstPtr inst, int stage_num,
-                  InstSeqNum squash_seq_num, unsigned tid)
+                  InstSeqNum squash_seq_num, ThreadID tid)
 {
     vector<int> slot_remove_list;
 
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index aba5a1b0c..8946ad5d3 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -144,7 +144,7 @@ class CacheUnit : public Resource
     void execute(int slot_num);
 
     void squash(DynInstPtr inst, int stage_num,
-                InstSeqNum squash_seq_num, unsigned tid);
+                InstSeqNum squash_seq_num, ThreadID tid);
 
     /** Processes cache completion event. */
     void processCacheCompletion(PacketPtr pkt);
diff --git a/src/cpu/inorder/resources/decode_unit.cc b/src/cpu/inorder/resources/decode_unit.cc
index d95b1d4bb..033c318f2 100644
--- a/src/cpu/inorder/resources/decode_unit.cc
+++ b/src/cpu/inorder/resources/decode_unit.cc
@@ -39,7 +39,7 @@ DecodeUnit::DecodeUnit(std::string res_name, int res_id, int res_width,
                        int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
     : Resource(res_name, res_id, res_width, res_latency, _cpu)
 {
-    for (int tid = 0; tid < MaxThreads; tid++) {
+    for (ThreadID tid = 0; tid < MaxThreads; tid++) {
         regDepMap[tid] = &cpu->archRegDepMap[tid];
     }
 }
@@ -50,10 +50,8 @@ DecodeUnit::execute(int slot_num)
     ResourceRequest* decode_req = reqMap[slot_num];
     DynInstPtr inst = reqMap[slot_num]->inst;
     Fault fault = reqMap[slot_num]->fault;
-    int tid, seq_num;
+    ThreadID tid = inst->readTid();
 
-    tid = inst->readTid();
-    seq_num = inst->seqNum;
     decode_req->fault = NoFault;
 
     switch (decode_req->cmd)
@@ -63,13 +61,17 @@ DecodeUnit::execute(int slot_num)
             bool done_sked = ThePipeline::createBackEndSchedule(inst);
 
             if (done_sked) {
-                DPRINTF(InOrderDecode, "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
-                    tid, seq_num);
+                DPRINTF(InOrderDecode,
+                    "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
+                    tid, inst->seqNum);
                 regDepMap[tid]->insert(inst);
                 decode_req->done();
             } else {
-                DPRINTF(Resource,"[tid:%i] Static Inst not available to decode. Unable to create "
-                        "schedule for instruction [sn:%i] \n", tid, inst->seqNum);
+                DPRINTF(Resource,
+                    "[tid:%i] Static Inst not available to decode.\n", tid);
+                DPRINTF(Resource,
+                    "Unable to create schedule for instruction [sn:%i] \n",
+                    inst->seqNum);
                 DPRINTF(InOrderStall, "STALL: \n");
                 decode_req->done(false);
             }
@@ -83,9 +85,11 @@ DecodeUnit::execute(int slot_num)
 
 
 void
-DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
+DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+                   ThreadID tid)
 {
-    DPRINTF(InOrderDecode, "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
+    DPRINTF(InOrderDecode,
+            "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
             tid, stage_num, squash_seq_num);
 
     //cpu->removeInstsUntil(squash_seq_num, tid);
diff --git a/src/cpu/inorder/resources/decode_unit.hh b/src/cpu/inorder/resources/decode_unit.hh
index 3813de6c4..1a700c211 100644
--- a/src/cpu/inorder/resources/decode_unit.hh
+++ b/src/cpu/inorder/resources/decode_unit.hh
@@ -57,7 +57,8 @@ class DecodeUnit : public Resource {
 
     virtual void execute(int slot_num);
 
-    void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
+    void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+                ThreadID tid);
 
     RegDepMap *regDepMap[ThePipeline::MaxThreads];
 
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index 16f00b1be..c9072b5d5 100644
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -63,7 +63,7 @@ ExecutionUnit::execute(int slot_num)
     ResourceRequest* exec_req = reqMap[slot_num];
     DynInstPtr inst = reqMap[slot_num]->inst;
     Fault fault = reqMap[slot_num]->fault;
-    int tid = inst->readTid();
+    ThreadID tid = inst->readTid();
     int seq_num = inst->seqNum;
 
     exec_req->fault = NoFault;
@@ -89,7 +89,7 @@ ExecutionUnit::execute(int slot_num)
                     // that got squashed.
                     if (inst->mispredicted()) {
                         int stage_num = exec_req->getStageNum();
-                        int tid = inst->readTid();
+                        ThreadID tid = inst->readTid();
 
                         // If it's a branch ...
                         if (inst->isDirectCtrl()) {
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index 69610ae58..bc809b040 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -41,7 +41,7 @@ FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
     : Resource(res_name, res_id, res_width, res_latency, _cpu),
       instSize(sizeof(MachInst))
 {
-    for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
+    for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
         delaySlotInfo[tid].numInsts = 0;
         delaySlotInfo[tid].targetReady = false;
 
@@ -68,7 +68,7 @@ FetchSeqUnit::execute(int slot_num)
     // for performance considerations
     ResourceRequest* fs_req = reqMap[slot_num];
     DynInstPtr inst = fs_req->inst;
-    int tid = inst->readTid();
+    ThreadID tid = inst->readTid();
     int stage_num = fs_req->getStageNum();
     int seq_num = inst->seqNum;
 
@@ -202,7 +202,7 @@ FetchSeqUnit::execute(int slot_num)
 }
 
 inline void
-FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid)
+FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
 {
     // Squash In Pipeline Stage
     cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
@@ -216,7 +216,7 @@ FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid)
 }
 void
 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
-                     InstSeqNum squash_seq_num, unsigned tid)
+                     InstSeqNum squash_seq_num, ThreadID tid)
 {
     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i.\n",
             tid, squash_stage);
@@ -302,7 +302,7 @@ FetchSeqUnit::FetchSeqEvent::process()
 
 
 void
-FetchSeqUnit::activateThread(unsigned tid)
+FetchSeqUnit::activateThread(ThreadID tid)
 {
     pcValid[tid] = true;
 
@@ -317,7 +317,7 @@ FetchSeqUnit::activateThread(unsigned tid)
 }
 
 void
-FetchSeqUnit::deactivateThread(unsigned tid)
+FetchSeqUnit::deactivateThread(ThreadID tid)
 {
     delaySlotInfo[tid].numInsts = 0;
     delaySlotInfo[tid].targetReady = false;
@@ -328,7 +328,7 @@ FetchSeqUnit::deactivateThread(unsigned tid)
     squashSeqNum[tid] = (InstSeqNum)-1;
     lastSquashCycle[tid] = 0;
 
-    std::list<unsigned>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
+    list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
                                               cpu->fetchPriorityList.end(),
                                               tid);
 
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.hh b/src/cpu/inorder/resources/fetch_seq_unit.hh
index 1885d1f11..3e18d47cb 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.hh
+++ b/src/cpu/inorder/resources/fetch_seq_unit.hh
@@ -56,8 +56,8 @@ class FetchSeqUnit : public Resource {
     virtual ~FetchSeqUnit() {}
 
     virtual void init();
-    virtual void activateThread(unsigned tid);
-    virtual void deactivateThread(unsigned tid);
+    virtual void activateThread(ThreadID tid);
+    virtual void deactivateThread(ThreadID tid);
     virtual void execute(int slot_num);
 
     /** Override default Resource squash sequence. This actually,
@@ -65,10 +65,10 @@ class FetchSeqUnit : public Resource {
      *  info
      */
     virtual void squash(DynInstPtr inst, int squash_stage,
-                        InstSeqNum squash_seq_num, unsigned tid);
+                        InstSeqNum squash_seq_num, ThreadID tid);
 
 
-    inline void squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid);
+    inline void squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid);
 
   protected:
     unsigned instSize;
diff --git a/src/cpu/inorder/resources/graduation_unit.cc b/src/cpu/inorder/resources/graduation_unit.cc
index 569401e4f..2d7cd5c8c 100644
--- a/src/cpu/inorder/resources/graduation_unit.cc
+++ b/src/cpu/inorder/resources/graduation_unit.cc
@@ -39,7 +39,7 @@ GraduationUnit::GraduationUnit(std::string res_name, int res_id, int res_width,
       lastCycleGrad(0), numCycleGrad(0)
       
 {
-    for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
+    for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
         nonSpecInstActive[tid] = &cpu->nonSpecInstActive[tid];
         nonSpecSeqNum[tid] = &cpu->nonSpecSeqNum[tid];
     }
@@ -51,10 +51,7 @@ GraduationUnit::execute(int slot_num)
     ResourceRequest* grad_req = reqMap[slot_num];
     DynInstPtr inst = reqMap[slot_num]->inst;
     Fault fault = reqMap[slot_num]->fault;
-    int tid, seq_num;
-
-    tid = inst->readTid();
-    seq_num = inst->seqNum;
+    ThreadID tid = inst->readTid();
     int stage_num = inst->resSched.top()->stageNum;
 
     grad_req->fault = NoFault;
@@ -70,15 +67,17 @@ GraduationUnit::execute(int slot_num)
                 lastCycleGrad = curTick;
                 numCycleGrad = 0;
             } else if (numCycleGrad > width) {
-                DPRINTF(InOrderGraduation, "Graduation bandwidth reached for this cycle.\n");
+                DPRINTF(InOrderGraduation,
+                        "Graduation bandwidth reached for this cycle.\n");
                 return;
             }
 
             // Make sure this is the last thing on the resource schedule
             assert(inst->resSched.size() == 1);
 
-            DPRINTF(InOrderGraduation, "[tid:%i] Graduating instruction [sn:%i].\n",
-                    tid, seq_num);
+            DPRINTF(InOrderGraduation,
+                    "[tid:%i] Graduating instruction [sn:%i].\n",
+                    tid, inst->seqNum);
 
             DPRINTF(RefCount, "Refcount = %i.\n", 0/*inst->curCount()*/);
 
@@ -87,8 +86,9 @@ GraduationUnit::execute(int slot_num)
             // @TODO: Fix this functionality. Probably too conservative.
             if (inst->isNonSpeculative()) {
                 *nonSpecInstActive[tid] = false;
-                DPRINTF(InOrderGraduation, "[tid:%i] Non-speculative instruction [sn:%i] has graduated.\n",
-                        tid, seq_num);
+                DPRINTF(InOrderGraduation,
+                        "[tid:%i] Non-speculative inst [sn:%i] graduated\n",
+                        tid, inst->seqNum);
             }
 
             if (inst->traceData) {
diff --git a/src/cpu/inorder/resources/inst_buffer.cc b/src/cpu/inorder/resources/inst_buffer.cc
index fafff1fa7..21df1d053 100644
--- a/src/cpu/inorder/resources/inst_buffer.cc
+++ b/src/cpu/inorder/resources/inst_buffer.cc
@@ -60,11 +60,9 @@ InstBuffer::execute(int slot_idx)
 {
     ResReqPtr ib_req = reqMap[slot_idx];
     DynInstPtr inst = ib_req->inst;
-    int tid, seq_num, stage_num;
+    ThreadID tid = inst->readTid();
+    int stage_num = ib_req->getStageNum();
 
-    tid = inst->readTid();
-    seq_num = inst->seqNum;
-    stage_num = ib_req->getStageNum();
     ib_req->fault = NoFault;
 
     switch (ib_req->cmd)
@@ -121,12 +119,12 @@ InstBuffer::execute(int slot_idx)
 
             if (instList.size() < width) {
                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into buffer.\n",
-                        tid, seq_num);
+                        tid, inst->seqNum);
                 insert(inst);
                 inserted = true;
             } else {
                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request because "
-                        "buffer is full.\n", tid, seq_num);
+                        "buffer is full.\n", tid, inst->seqNum);
 
 
                 std::list<DynInstPtr>::iterator list_it = instList.begin();
@@ -145,7 +143,7 @@ InstBuffer::execute(int slot_idx)
       case RemoveInst:
         {
             DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from buffer.\n",
-                    tid, seq_num);
+                    tid, inst->seqNum);
             remove(inst);
             ib_req->done();
         }
@@ -180,20 +178,20 @@ InstBuffer::remove(DynInstPtr inst)
 }
 
 void
-InstBuffer::pop(unsigned tid)
+InstBuffer::pop(ThreadID tid)
 {
     instList.pop_front();
 }
 
 ThePipeline::DynInstPtr
-InstBuffer::top(unsigned tid)
+InstBuffer::top(ThreadID tid)
 {
     return instList.front();
 }
 
 void
 InstBuffer::squash(DynInstPtr inst, int stage_num,
-                   InstSeqNum squash_seq_num, unsigned tid)
+                   InstSeqNum squash_seq_num, ThreadID tid)
 {
     queue<list<DynInstPtr>::iterator> remove_list;
     list<DynInstPtr>::iterator list_it = instList.begin();
diff --git a/src/cpu/inorder/resources/inst_buffer.hh b/src/cpu/inorder/resources/inst_buffer.hh
index baadd42ff..7342df66f 100644
--- a/src/cpu/inorder/resources/inst_buffer.hh
+++ b/src/cpu/inorder/resources/inst_buffer.hh
@@ -67,12 +67,12 @@ class InstBuffer : public Resource {
 
     virtual void remove(DynInstPtr inst);
 
-    virtual void pop(unsigned tid);
+    virtual void pop(ThreadID tid);
 
-    virtual DynInstPtr top(unsigned tid);
+    virtual DynInstPtr top(ThreadID tid);
 
     virtual void squash(DynInstPtr inst, int stage_num,
-                        InstSeqNum squash_seq_num, unsigned tid);
+                        InstSeqNum squash_seq_num, ThreadID tid);
   protected:
     /** List of instructions this resource is currently
      *  processing.
diff --git a/src/cpu/inorder/resources/inst_buffer_new.cc b/src/cpu/inorder/resources/inst_buffer_new.cc
index 7e2c98837..cc534ef3e 100644
--- a/src/cpu/inorder/resources/inst_buffer_new.cc
+++ b/src/cpu/inorder/resources/inst_buffer_new.cc
@@ -67,7 +67,7 @@ InstBuffer::execute(int slot_idx)
     assert(ib_req);
 
     DynInstPtr inst = ib_req->inst;
-    int tid = inst->readTid();
+    ThreadID tid = inst->readTid();
     int seq_num = inst->seqNum;
     ib_req->fault = NoFault;
 
@@ -128,7 +128,7 @@ InstBuffer::top()
 { return instList.front(); }
 
 void
-InstBuffer::squash(InstSeqNum squash_seq_num, unsigned tid)
+InstBuffer::squash(InstSeqNum squash_seq_num, ThreadID tid)
 {
     list<DynInstPtr>::iterator list_it = instList.begin();
     list<DynInstPtr>::iterator list_end = instList.end();
diff --git a/src/cpu/inorder/resources/inst_buffer_new.hh b/src/cpu/inorder/resources/inst_buffer_new.hh
index e374fa109..b1d5a7b09 100644
--- a/src/cpu/inorder/resources/inst_buffer_new.hh
+++ b/src/cpu/inorder/resources/inst_buffer_new.hh
@@ -71,7 +71,7 @@ class InstBuffer : public Resource {
 
     virtual DynInstPtr top();
 
-    virtual void squash(InstSeqNum squash_seq_num, unsigned tid);
+    virtual void squash(InstSeqNum squash_seq_num, ThreadID tid);
 
   protected:
     /** List of instructions this resource is currently
diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc
index df9d4c293..7592c0260 100644
--- a/src/cpu/inorder/resources/mult_div_unit.cc
+++ b/src/cpu/inorder/resources/mult_div_unit.cc
@@ -174,7 +174,7 @@ MultDivUnit::execute(int slot_num)
     DynInstPtr inst = reqMap[slot_num]->inst;
     Fault fault = reqMap[slot_num]->fault;
  
-    //int tid = inst->readTid();
+    //ThreadID tid = inst->readTid();
     //int seq_num = inst->seqNum;
 
     switch (mult_div_req->cmd)
@@ -248,7 +248,7 @@ MultDivUnit::exeMulDiv(int slot_num)
     ResourceRequest* mult_div_req = reqMap[slot_num];
     DynInstPtr inst = reqMap[slot_num]->inst;
     Fault fault = reqMap[slot_num]->fault;
-    int tid = inst->readTid();
+    ThreadID tid = inst->readTid();
     int seq_num = inst->seqNum;
 
     fault = inst->execute();
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 1ce8ff8c2..95bade36a 100644
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -101,11 +101,9 @@ TLBUnit::execute(int slot_idx)
     assert(tlb_req != 0x0);
 
     DynInstPtr inst = tlb_req->inst;
-    int tid, seq_num, stage_num;
-
-    tid = inst->readTid();
-    seq_num = inst->seqNum;
-    stage_num = tlb_req->getStageNum();
+    ThreadID tid = inst->readTid();
+    int seq_num = inst->seqNum;
+    int stage_num = tlb_req->getStageNum();
 
     tlb_req->fault = NoFault;
 
@@ -202,7 +200,7 @@ TLBUnitEvent::process()
 {
     DynInstPtr inst = resource->reqMap[slotIdx]->inst;
     int stage_num = resource->reqMap[slotIdx]->getStageNum();
-    int tid = inst->threadNumber;
+    ThreadID tid = inst->threadNumber;
 
     DPRINTF(InOrderTLB, "Waking up from TLB Miss caused by [sn:%i].\n",
             inst->seqNum);
@@ -224,7 +222,7 @@ TLBUnitEvent::process()
 
 void
 TLBUnit::squash(DynInstPtr inst, int stage_num,
-                   InstSeqNum squash_seq_num, unsigned tid)
+                   InstSeqNum squash_seq_num, ThreadID tid)
 {
      //@TODO: Figure out a way to consolidate common parts
      //       of this squash code
diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh
index 8f0291b48..1c08bd822 100644
--- a/src/cpu/inorder/resources/tlb_unit.hh
+++ b/src/cpu/inorder/resources/tlb_unit.hh
@@ -67,7 +67,8 @@ class TLBUnit : public Resource
 
     virtual void execute(int slot_num);
 
-    void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
+    void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+                ThreadID tid);
 
     bool tlbBlocked[ThePipeline::MaxThreads];
 
diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc
index 53145640e..b30a3a1bf 100644
--- a/src/cpu/inorder/resources/use_def.cc
+++ b/src/cpu/inorder/resources/use_def.cc
@@ -45,7 +45,7 @@ UseDefUnit::UseDefUnit(string res_name, int res_id, int res_width,
     : Resource(res_name, res_id, res_width, res_latency, _cpu),
       maxSeqNum((InstSeqNum)-1)
 {
-    for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
+    for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
         nonSpecInstActive[tid] = &cpu->nonSpecInstActive[tid];
         nonSpecSeqNum[tid] = &cpu->nonSpecSeqNum[tid];
 
@@ -99,7 +99,7 @@ UseDefUnit::execute(int slot_idx)
     assert(ud_req);
 
     DynInstPtr inst = ud_req->inst;
-    int tid = inst->readTid();
+    ThreadID tid = inst->readTid();
     int seq_num = inst->seqNum;
     int ud_idx = ud_req->useDefIdx;
 
@@ -306,7 +306,8 @@ UseDefUnit::execute(int slot_idx)
 }
 
 void
-UseDefUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
+UseDefUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
+                   ThreadID tid)
 {
     DPRINTF(InOrderUseDef, "[tid:%i]: Updating Due To Squash After [sn:%i].\n",
             tid, squash_seq_num);
diff --git a/src/cpu/inorder/resources/use_def.hh b/src/cpu/inorder/resources/use_def.hh
index 51ec2c3f2..6c76d8ab5 100644
--- a/src/cpu/inorder/resources/use_def.hh
+++ b/src/cpu/inorder/resources/use_def.hh
@@ -65,7 +65,8 @@ class UseDefUnit : public Resource {
 
     virtual void execute(int slot_num);
 
-    virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
+    virtual void squash(DynInstPtr inst, int stage_num,
+                        InstSeqNum squash_seq_num, ThreadID tid);
 
     const InstSeqNum maxSeqNum;
 
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index 0cac51559..a1e9b5948 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -175,7 +175,7 @@ InOrderThreadContext::readFloatRegBits(int reg_idx)
 }
 
 uint64_t
-InOrderThreadContext::readRegOtherThread(int reg_idx, unsigned tid)
+InOrderThreadContext::readRegOtherThread(int reg_idx, ThreadID tid)
 {
     return cpu->readRegOtherThread(reg_idx, tid);
 }
@@ -212,7 +212,8 @@ InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
 }
 
 void
-InOrderThreadContext::setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid)
+InOrderThreadContext::setRegOtherThread(int misc_reg, const MiscReg &val,
+                                        ThreadID tid)
 {
     cpu->setRegOtherThread(misc_reg, val, tid);
 }
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index cde377dfc..f3cf3ec44 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -160,7 +160,7 @@ class InOrderThreadContext : public ThreadContext
 
     virtual FloatRegBits readFloatRegBits(int reg_idx);
 
-    virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid);
+    virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
 
     /** Sets an integer register to a value. */
     virtual void setIntReg(int reg_idx, uint64_t val);
@@ -173,7 +173,8 @@ class InOrderThreadContext : public ThreadContext
 
     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 
-    virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid);
+    virtual void setRegOtherThread(int misc_reg, const MiscReg &val,
+                                   ThreadID tid);
 
     /** Reads this thread's PC. */
     virtual uint64_t readPC()
diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh
index eb4fe40b2..803659487 100644
--- a/src/cpu/inorder/thread_state.hh
+++ b/src/cpu/inorder/thread_state.hh
@@ -67,8 +67,10 @@ class InOrderThreadState : public ThreadState {
     bool trapPending;
 
 
-    InOrderThreadState(InOrderCPU *_cpu, int _thread_num, Process *_process, int _asid)
-        : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), 0/*_thread_num*/, _process, 0/*_asid*/),
+    InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num,
+                       Process *_process, int _asid)
+        : ThreadState(reinterpret_cast<BaseCPU*>(_cpu), 0/*_thread_num*/,
+                      _process, 0/*_asid*/),
           cpu(_cpu), inSyscall(0), trapPending(0)
     { }