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author | Gabe Black <gblack@eecs.umich.edu> | 2012-05-25 00:53:37 -0700 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2012-05-25 00:53:37 -0700 |
commit | 82a228bd4348f2788151630fab0160acc368b4ff (patch) | |
tree | 79a685753c6f72eb6b76784d3d2e459b907b5ddb /src/cpu/inorder | |
parent | 49da0497d3a4695ca613e6e47161f41d74ce9d32 (diff) | |
download | gem5-82a228bd4348f2788151630fab0160acc368b4ff.tar.xz |
Decode: Make the Decoder class defined per ISA.
--HG--
rename : src/cpu/decode.cc => src/arch/generic/decoder.cc
rename : src/cpu/decode.hh => src/arch/generic/decoder.hh
Diffstat (limited to 'src/cpu/inorder')
-rw-r--r-- | src/cpu/inorder/cpu.cc | 2 | ||||
-rw-r--r-- | src/cpu/inorder/cpu.hh | 2 | ||||
-rw-r--r-- | src/cpu/inorder/resources/fetch_unit.hh | 4 | ||||
-rw-r--r-- | src/cpu/inorder/thread_context.hh | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 7e75dfbb8..9ad0a2680 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -1772,7 +1772,7 @@ InOrderCPU::getDTBPtr() return resPool->getDataUnit()->tlb(); } -Decoder * +TheISA::Decoder * InOrderCPU::getDecoderPtr() { return &resPool->getInstUnit()->decoder; diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index bb52c6023..29fe6bc3b 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -342,7 +342,7 @@ class InOrderCPU : public BaseCPU TheISA::TLB *getITBPtr(); TheISA::TLB *getDTBPtr(); - Decoder *getDecoderPtr(); + TheISA::Decoder *getDecoderPtr(); /** Accessor Type for the SkedCache */ typedef uint32_t SkedID; diff --git a/src/cpu/inorder/resources/fetch_unit.hh b/src/cpu/inorder/resources/fetch_unit.hh index 6d734d7e6..eb99cd570 100644 --- a/src/cpu/inorder/resources/fetch_unit.hh +++ b/src/cpu/inorder/resources/fetch_unit.hh @@ -36,10 +36,10 @@ #include <string> #include <vector> +#include "arch/decoder.hh" #include "arch/predecoder.hh" #include "arch/tlb.hh" #include "config/the_isa.hh" -#include "cpu/decode.hh" #include "cpu/inorder/resources/cache_unit.hh" #include "cpu/inorder/inorder_dyn_inst.hh" #include "cpu/inorder/pipeline_traits.hh" @@ -89,7 +89,7 @@ class FetchUnit : public CacheUnit void trap(Fault fault, ThreadID tid, DynInstPtr inst); - Decoder decoder; + TheISA::Decoder decoder; private: void squashCacheRequest(CacheReqPtr req_ptr); diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index 6f9bc5dac..b7d0dda9c 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -83,7 +83,7 @@ class InOrderThreadContext : public ThreadContext */ CheckerCPU *getCheckerCpuPtr() { return NULL; } - Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); } + TheISA::Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); } System *getSystemPtr() { return cpu->system; } |