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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:15:34 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:15:34 -0800 |
| commit | a1aba01a02a8c1261120de83d8fbfd6624f0cb17 (patch) | |
| tree | 9d5e0abec98c0879b03a4d34d0862731424408f5 /src/cpu/inorder | |
| parent | f3090e5b704a2b7a02a736ec8601cd961fe3a865 (diff) | |
| download | gem5-a1aba01a02a8c1261120de83d8fbfd6624f0cb17.tar.xz | |
CPU: Get rid of translate... functions from various interface classes.
Diffstat (limited to 'src/cpu/inorder')
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 18 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/tlb_unit.cc | 6 |
2 files changed, 4 insertions, 20 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 6c1cdc9dc..4a7dfb404 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -498,24 +498,6 @@ class InOrderCPU : public BaseCPU /** Debug function to print all instructions on the list. */ void dumpInsts(); - /** Translates instruction requestion in syscall emulation mode. */ - Fault translateInstReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data read request in syscall emulation mode. */ - Fault translateDataReadReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data write request in syscall emulation mode. */ - Fault translateDataWriteReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - /** Forwards an instruction read to the appropriate data * resource (indexes into Resource Pool thru "dataPortIdx") */ diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc index 9b0decedb..4eeb4727b 100644 --- a/src/cpu/inorder/resources/tlb_unit.cc +++ b/src/cpu/inorder/resources/tlb_unit.cc @@ -98,7 +98,8 @@ TLBUnit::execute(int slot_idx) case FetchLookup: { tlb_req->fault = - this->cpu->translateInstReq(tlb_req->memReq, cpu->thread[tid]); + this->cpu->itb->translate(tlb_req->memReq, + cpu->thread[tid]->getTC()); if (tlb_req->fault != NoFault) { DPRINTF(Resource, "[tid:%i]: %s encountered while translating " @@ -128,7 +129,8 @@ TLBUnit::execute(int slot_idx) tid, seq_num, tlb_req->memReq->getVaddr()); tlb_req->fault = - this->cpu->translateInstReq(tlb_req->memReq, cpu->thread[tid]); + this->cpu->itb->translate(tlb_req->memReq, + cpu->thread[tid]->getTC()); if (tlb_req->fault != NoFault) { DPRINTF(Resource, "[tid:%i]: %s encountered while translating " |