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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 21:44:15 -0700 |
| commit | bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350 (patch) | |
| tree | 5492dc138704c1c3da4592a42f6a45be904e0188 /src/cpu/inorder | |
| parent | 089b3840865f816493a33f2ccf987307d0a79f87 (diff) | |
| download | gem5-bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350.tar.xz | |
Mem: Change isLlsc to isLLSC.
Diffstat (limited to 'src/cpu/inorder')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index ceaaf3532..772437638 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -355,7 +355,7 @@ CacheUnit::doDataAccess(DynInstPtr inst) Request *memReq = cache_req->dataPkt->req; - if (cache_req->dataPkt->isWrite() && memReq->isLlsc()) { + if (cache_req->dataPkt->isWrite() && memReq->isLLSC()) { assert(cache_req->inst->isStoreConditional()); DPRINTF(InOrderCachePort, "Evaluating Store Conditional access\n"); do_access = TheISA::handleLockedWrite(cpu, memReq); @@ -395,7 +395,7 @@ CacheUnit::doDataAccess(DynInstPtr inst) cacheStatus = cacheWaitResponse; cacheBlocked = false; } - } else if (!do_access && memReq->isLlsc()){ + } else if (!do_access && memReq->isLLSC()){ // Store-Conditional instructions complete even if they "failed" assert(cache_req->inst->isStoreConditional()); cache_req->setCompleted(true); @@ -471,7 +471,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt) if (inst->isLoad()) { assert(cache_pkt->isRead()); - if (cache_pkt->req->isLlsc()) { + if (cache_pkt->req->isLLSC()) { DPRINTF(InOrderCachePort, "[tid:%u]: Handling Load-Linked for [sn:%u]\n", tid, inst->seqNum); |