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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:33 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:33 -0400 |
| commit | 76c60c5f9309af239f7fbe65e760e65f6c84bbe5 (patch) | |
| tree | 015ce84a74d035cc0fecbc12a90c0f8df8cf1506 /src/cpu/inorder | |
| parent | 0b7ca66919ee2a90683df1e3340f08fe6c30da5e (diff) | |
| download | gem5-76c60c5f9309af239f7fbe65e760e65f6c84bbe5.tar.xz | |
inorder: use m5_hash_map for skedCache
since we dont care about if the cache of instruction schedules is sorted or not,
then the hash map should be faster
Diffstat (limited to 'src/cpu/inorder')
| -rw-r--r-- | src/cpu/inorder/cpu.cc | 8 | ||||
| -rw-r--r-- | src/cpu/inorder/cpu.hh | 4 |
2 files changed, 5 insertions, 7 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 97748deba..bb9b5c3c6 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -358,10 +358,8 @@ InOrderCPU::~InOrderCPU() { delete resPool; - std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_it = - skedCache.begin(); - std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_end = - skedCache.end(); + SkedCacheIt sked_it = skedCache.begin(); + SkedCacheIt sked_end = skedCache.end(); while (sked_it != sked_end) { delete (*sked_it).second; @@ -370,7 +368,7 @@ InOrderCPU::~InOrderCPU() skedCache.clear(); } -std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache; +m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache; RSkedPtr InOrderCPU::createFrontEndSked() diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index af2fa5ced..c4a38d071 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -300,9 +300,9 @@ class InOrderCPU : public BaseCPU typedef uint32_t SkedID; /** Cache of Instruction Schedule using the instruction's name as a key */ - static std::map<SkedID, ThePipeline::RSkedPtr> skedCache; + static m5::hash_map<SkedID, ThePipeline::RSkedPtr> skedCache; - typedef std::map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt; + typedef m5::hash_map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt; /** Initialized to last iterator in map, signifying a invalid entry on map searches |