CPU: Merge the predecoder and decoder.

These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.

--HG--
rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc

7 files changed, 15 insertions, 20 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 9ad0a2680..3c27cf4b2 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1773,9 +1773,9 @@ InOrderCPU::getDTBPtr()
 }
 
 TheISA::Decoder *
-InOrderCPU::getDecoderPtr()
+InOrderCPU::getDecoderPtr(unsigned tid)
 {
-    return &resPool->getInstUnit()->decoder;
+    return resPool->getInstUnit()->decoder[tid];
 }
 
 Fault
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 29fe6bc3b..615d0eb90 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -342,7 +342,7 @@ class InOrderCPU : public BaseCPU
     TheISA::TLB *getITBPtr();
     TheISA::TLB *getDTBPtr();
 
-    TheISA::Decoder *getDecoderPtr();
+    TheISA::Decoder *getDecoderPtr(unsigned tid);
 
     /** Accessor Type for the SkedCache */
     typedef uint32_t SkedID;
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index a4dc23d47..21d7bb6e2 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -34,7 +34,6 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/locked_mem.hh"
-#include "arch/predecoder.hh"
 #include "arch/utility.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/resources/cache_unit.hh"
diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index f0878d24d..dda39a7a5 100644
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -36,7 +36,6 @@
 #include <string>
 #include <vector>
 
-#include "arch/predecoder.hh"
 #include "arch/tlb.hh"
 #include "base/hashmap.hh"
 #include "config/the_isa.hh"
diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc
index cc4b8b53e..07669ef2a 100644
--- a/src/cpu/inorder/resources/fetch_unit.cc
+++ b/src/cpu/inorder/resources/fetch_unit.cc
@@ -34,7 +34,6 @@
 
 #include "arch/isa_traits.hh"
 #include "arch/locked_mem.hh"
-#include "arch/predecoder.hh"
 #include "arch/utility.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/resources/cache_unit.hh"
@@ -60,7 +59,7 @@ FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
       instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
 {
     for (int tid = 0; tid < MaxThreads; tid++)
-        predecoder[tid] = new Predecoder(NULL);
+        decoder[tid] = new Decoder(NULL);
 }
 
 FetchUnit::~FetchUnit()
@@ -92,7 +91,6 @@ void
 FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
                           DynInstPtr inst)
 {
-    ExtMachInst ext_inst;
     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
     Addr fetch_addr = inst->getMemAddr();
     unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
@@ -111,13 +109,11 @@ FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
     MachInst mach_inst =
         TheISA::gtoh(fetchInsts[fetch_offset]);
 
-    predecoder[tid]->setTC(cpu->thread[tid]->getTC());
-    predecoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
-    assert(predecoder[tid]->extMachInstReady());
-    ext_inst = predecoder[tid]->getExtMachInst(instPC);
-
+    decoder[tid]->setTC(cpu->thread[tid]->getTC());
+    decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
+    assert(decoder[tid]->instReady());
+    inst->setStaticInst(decoder[tid]->decode(instPC));
     inst->pcState(instPC);
-    inst->setStaticInst(decoder.decode(ext_inst, instPC.instAddr()));
 }
 
 void
@@ -582,7 +578,7 @@ void
 FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 {
     //@todo: per thread?
-    predecoder[tid]->reset();
+    decoder[tid]->reset();
 
     //@todo: squash using dummy inst seq num
     squash(NULL, NumStages - 1, 0, tid);
diff --git a/src/cpu/inorder/resources/fetch_unit.hh b/src/cpu/inorder/resources/fetch_unit.hh
index eb99cd570..82d5d99e0 100644
--- a/src/cpu/inorder/resources/fetch_unit.hh
+++ b/src/cpu/inorder/resources/fetch_unit.hh
@@ -37,7 +37,6 @@
 #include <vector>
 
 #include "arch/decoder.hh"
-#include "arch/predecoder.hh"
 #include "arch/tlb.hh"
 #include "config/the_isa.hh"
 #include "cpu/inorder/resources/cache_unit.hh"
@@ -89,7 +88,7 @@ class FetchUnit : public CacheUnit
 
     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 
-    TheISA::Decoder decoder;
+    TheISA::Decoder *decoder[ThePipeline::MaxThreads];
 
   private:
     void squashCacheRequest(CacheReqPtr req_ptr);
@@ -129,8 +128,6 @@ class FetchUnit : public CacheUnit
 
     int fetchBuffSize;
 
-    TheISA::Predecoder *predecoder[ThePipeline::MaxThreads];
-
     /** Valid Cache Blocks*/
     std::list<FetchBlock*> fetchBuffer;
 
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index b7d0dda9c..9b588cde0 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -83,7 +83,11 @@ class InOrderThreadContext : public ThreadContext
      */
     CheckerCPU *getCheckerCpuPtr() { return NULL; }
 
-    TheISA::Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
+    TheISA::Decoder *
+    getDecoderPtr()
+    {
+        return cpu->getDecoderPtr(thread->contextId());
+    }
 
     System *getSystemPtr() { return cpu->system; }