MEM: Separate requests and responses for timing accesses

This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.

For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).

The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.

With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.

3 files changed, 4 insertions, 6 deletions

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 04176c54f..7e75dfbb8 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -88,10 +88,8 @@ InOrderCPU::CachePort::CachePort(CacheUnit *_cacheUnit) :
 { }
 
 bool
-InOrderCPU::CachePort::recvTiming(Packet *pkt)
+InOrderCPU::CachePort::recvTimingResp(Packet *pkt)
 {
-    assert(pkt->isResponse());
-
     if (pkt->isError())
         DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
                 pkt->getAddr());
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 06d733d85..bb52c6023 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -170,13 +170,13 @@ class InOrderCPU : public BaseCPU
       protected:
 
         /** Timing version of receive */
-        bool recvTiming(PacketPtr pkt);
+        bool recvTimingResp(PacketPtr pkt);
 
         /** Handles doing a retry of a failed timing request. */
         void recvRetry();
 
         /** Ignoring snoops for now. */
-        bool recvTimingSnoop(PacketPtr pkt) { return true; }
+        void recvTimingSnoopReq(PacketPtr pkt) { }
     };
 
     /** Define TickEvent for the CPU */
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index a5bb9cd24..a4dc23d47 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -873,7 +873,7 @@ CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res,
             tid, inst->seqNum, cache_req->dataPkt->getAddr());
 
     if (do_access) {
-        if (!cachePort->sendTiming(cache_req->dataPkt)) {
+        if (!cachePort->sendTimingReq(cache_req->dataPkt)) {
             DPRINTF(InOrderCachePort,
                     "[tid:%i] [sn:%i] cannot access cache, because port "
                     "is blocked. now waiting to retry request\n", tid,