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| author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:41 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:41 -0400 |
| commit | 5ef0b7a9db3c6ec4ca191c2e9381719e1e694873 (patch) | |
| tree | 718fdaf81b288b91bbac7eb2a8bae285d2dc39ac /src/cpu/inorder | |
| parent | 716e447da8424386f2c3448c17891927aeb49f67 (diff) | |
| download | gem5-5ef0b7a9db3c6ec4ca191c2e9381719e1e694873.tar.xz | |
inorder/dtb: make sure DTB translate correct address
The DTB expects the correct PC in the ThreadContext
but how if the memory accesses are speculative? Shouldn't
we send along the requestor's PC to the translate functions?
Diffstat (limited to 'src/cpu/inorder')
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 7a24348fc..39afd296e 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -426,9 +426,16 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size, ThreadID tid = inst->readTid(); setupMemRequest(inst, cache_req, acc_size, flags); + + //@todo: HACK: the DTB expects the correct PC in the ThreadContext + // but how if the memory accesses are speculative? Shouldn't + // we send along the requestor's PC to the translate functions? + ThreadContext *tc = cpu->thread[tid]->getTC(); + PCState old_pc = tc->pcState(); + tc->pcState() = inst->pcState(); inst->fault = - _tlb->translateAtomic(cache_req->memReq, - cpu->thread[tid]->getTC(), tlb_mode); + _tlb->translateAtomic(cache_req->memReq, tc, tlb_mode); + tc->pcState() = old_pc; if (inst->fault != NoFault) { DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating " |