arch, cpu: Factor out the ExecContext into a proper base class

We currently generate and compile one version of the ISA code per CPU
model. This is obviously wasting a lot of resources at compile
time. This changeset factors out the interface into a separate
ExecContext class, which also serves as documentation for the
interface between CPUs and the ISA code. While doing so, this
changeset also fixes up interface inconsistencies between the
different CPU models.

The main argument for using one set of ISA code per CPU model has
always been performance as this avoid indirect branches in the
generated code. However, this argument does not hold water. Booting
Linux on a simulated ARM system running in atomic mode
(opt/10.linux-boot/realview-simple-atomic) is actually 2% faster
(compiled using clang 3.4) after applying this patch. Additionally,
compilation time is decreased by 35%.

3 files changed, 37 insertions, 19 deletions

diff --git a/src/cpu/inorder/SConsopts b/src/cpu/inorder/SConsopts
index 709051407..f6b8917c6 100644
--- a/src/cpu/inorder/SConsopts
+++ b/src/cpu/inorder/SConsopts
@@ -30,7 +30,4 @@
 
 Import('*')
 
-CpuModel('InOrderCPU', 'inorder_cpu_exec.cc',
-         '#include "cpu/inorder/inorder_dyn_inst.hh"',
-         { 'CPU_exec_context': 'InOrderDynInst' },
-         default=True)
+CpuModel('InOrderCPU', default=True)
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index 86dbdf97c..d0d308f7a 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -469,7 +469,7 @@ InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
 }
 
 MiscReg
-InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
+InOrderDynInst::readRegOtherThread(int reg_idx, ThreadID tid)
 {
     if (tid == -1) {
         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
@@ -544,8 +544,7 @@ InOrderDynInst::setMiscReg(int misc_reg, const MiscReg &val)
 }
 
 void
-InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
-                                  ThreadID tid)
+InOrderDynInst::setRegOtherThread(int reg_idx, MiscReg val, ThreadID tid)
 {
     if (tid == InvalidThreadID) {
         tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 578fd604a..759da4b04 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -45,6 +45,7 @@
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "config/the_isa.hh"
+#include "cpu/exec_context.hh"
 #include "cpu/inorder/inorder_trace.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "cpu/inorder/resource.hh"
@@ -73,7 +74,7 @@
 class ResourceRequest;
 class Packet;
 
-class InOrderDynInst : public RefCounted
+class InOrderDynInst : public ExecContext, public RefCounted
 {
   public:
     // Binary machine instruction type.
@@ -543,7 +544,7 @@ class InOrderDynInst : public RefCounted
     //
     ////////////////////////////////////////////////////////////
     /** Read the PC of this instruction. */
-    const TheISA::PCState &pcState() const { return pc; }
+    TheISA::PCState pcState() const { return pc; }
 
     /** Sets the PC of this instruction. */
     void pcState(const TheISA::PCState &_pc) { pc = _pc; }
@@ -649,10 +650,10 @@ class InOrderDynInst : public RefCounted
     { return memAddr; }
 
     /** Sets the effective address. */
-    void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
+    void setEA(Addr ea) { instEffAddr = ea; eaCalcDone = true; }
 
     /** Returns the effective address. */
-    const Addr &getEA() const { return instEffAddr; }
+    Addr getEA() const { return instEffAddr; }
 
     /** Returns whether or not the eff. addr. calculation has been completed.*/
     bool doneEACalc() { return eaCalcDone; }
@@ -854,7 +855,10 @@ class InOrderDynInst : public RefCounted
      *  language (which is why the name isnt readIntSrc(...)) Note: That
      *  the source reg. value is set using the setSrcReg() function.
      */
-    IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
+    IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid);
+    IntReg readIntRegOperand(const StaticInst *si, int idx) {
+        return readIntRegOperand(si, idx, 0);
+    }
     FloatReg readFloatRegOperand(const StaticInst *si, int idx);
     TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
     MiscReg readMiscReg(int misc_reg);
@@ -899,24 +903,21 @@ class InOrderDynInst : public RefCounted
     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
     void setFloatRegOperandBits(const StaticInst *si, int idx,
             TheISA::FloatRegBits val);
-    void setCCRegOperand(const StaticInst *si, int idx, CCReg val);
     void setMiscReg(int misc_reg, const MiscReg &val);
     void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
     void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
     void setMiscRegOperandNoEffect(const StaticInst *si, int idx,
                                    const MiscReg &val);
 
-    virtual uint64_t readRegOtherThread(unsigned idx,
-                                        ThreadID tid = InvalidThreadID);
-    virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
-                                   ThreadID tid = InvalidThreadID);
+    MiscReg readRegOtherThread(int idx, ThreadID tid);
+    void setRegOtherThread(int idx, MiscReg val, ThreadID tid);
 
     /** Returns the number of consecutive store conditional failures. */
-    unsigned readStCondFailures()
+    unsigned int readStCondFailures() const
     { return thread->storeCondFailures; }
 
     /** Sets the number of consecutive store conditional failures. */
-    void setStCondFailures(unsigned sc_failures)
+    void setStCondFailures(unsigned int sc_failures)
     { thread->storeCondFailures = sc_failures; }
 
     //////////////////////////////////////////////////////////////
@@ -1063,6 +1064,27 @@ class InOrderDynInst : public RefCounted
     void dump(std::string &outstring);
 
     //inline int curCount() { return curCount(); }
+
+
+    CCReg readCCRegOperand(const StaticInst *si, int idx) {
+        panic("readCCRegOperand unimplemented");
+    }
+
+    void setCCRegOperand(const StaticInst *si, int idx, CCReg val) {
+        panic("setCCRegOperand unimplemented");
+    }
+
+    void setPredicate(bool val) {
+        panic("setPredicate unimplemented");
+    }
+
+    bool readPredicate() {
+        panic("readPredicate unimplemented");
+    }
+
+    void demapPage(Addr vaddr, uint64_t asn) {
+        panic("demapPage unimplemented");
+    }
 };