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authorRekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>2017-04-05 13:24:00 -0500
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-05 14:43:49 +0000
commit00da08902918da13fccc3f2266b7b2f5d0080708 (patch)
treeb495a0ceba7e073adca005cf84a7575d0aad5f27 /src/cpu/inst_res.hh
parent0747a432d25ade2c197ca6393270e12606419872 (diff)
downloadgem5-00da08902918da13fccc3f2266b7b2f5d0080708.tar.xz
cpu: Added interface for vector reg file
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
Diffstat (limited to 'src/cpu/inst_res.hh')
-rw-r--r--src/cpu/inst_res.hh52
1 files changed, 52 insertions, 0 deletions
diff --git a/src/cpu/inst_res.hh b/src/cpu/inst_res.hh
index f6f14fe19..9b6a23d95 100644
--- a/src/cpu/inst_res.hh
+++ b/src/cpu/inst_res.hh
@@ -43,17 +43,24 @@
#include <type_traits>
#include "arch/generic/types.hh"
+#include "arch/generic/vec_reg.hh"
class InstResult {
+ using VecRegContainer = TheISA::VecRegContainer;
+ using VecElem = TheISA::VecElem;
public:
union MultiResult {
uint64_t integer;
double dbl;
+ VecRegContainer vector;
+ VecElem vecElem;
MultiResult() {}
};
enum class ResultType {
Scalar,
+ VecElem,
+ VecReg,
NumResultTypes,
Invalid
};
@@ -77,7 +84,32 @@ class InstResult {
result.dbl = i;
}
}
+ /** Vector result. */
+ explicit InstResult(const VecRegContainer& v, const ResultType& t)
+ : type(t) { result.vector = v; }
+ InstResult& operator=(const InstResult& that) {
+ type = that.type;
+ switch (type) {
+ /* Given that misc regs are not written to, there may be invalids in
+ * the result stack. */
+ case ResultType::Invalid:
+ break;
+ case ResultType::Scalar:
+ result.integer = that.result.integer;
+ break;
+ case ResultType::VecElem:
+ result.vecElem = that.result.vecElem;
+ break;
+ case ResultType::VecReg:
+ result.vector = that.result.vector;
+ break;
+ default:
+ panic("Assigning result from unknown result type");
+ break;
+ }
+ return *this;
+ }
/**
* Result comparison
* Two invalid results always differ.
@@ -88,6 +120,10 @@ class InstResult {
switch (type) {
case ResultType::Scalar:
return result.integer == that.result.integer;
+ case ResultType::VecElem:
+ return result.vecElem == that.result.vecElem;
+ case ResultType::VecReg:
+ return result.vector == that.result.vector;
case ResultType::Invalid:
return false;
default:
@@ -103,6 +139,10 @@ class InstResult {
/** @{ */
/** Is this a scalar result?. */
bool isScalar() const { return type == ResultType::Scalar; }
+ /** Is this a vector result?. */
+ bool isVector() const { return type == ResultType::VecReg; }
+ /** Is this a vector element result?. */
+ bool isVecElem() const { return type == ResultType::VecElem; }
/** Is this a valid result?. */
bool isValid() const { return type != ResultType::Invalid; }
/** @} */
@@ -125,6 +165,18 @@ class InstResult {
{
return result.integer;
}
+ const VecRegContainer&
+ asVector() const
+ {
+ panic_if(!isVector(), "Converting scalar (or invalid) to vector!!");
+ return result.vector;
+ }
+ const VecElem&
+ asVectorElem() const
+ {
+ panic_if(!isVecElem(), "Converting scalar (or invalid) to vector!!");
+ return result.vecElem;
+ }
/** @} */
};