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| author | Chuan Zhu <chuan.zhu@arm.com> | 2018-01-15 22:03:47 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-18 14:42:10 +0000 |
| commit | fcec1bf88c0f2e14f3c0c2dd59475757a7a6b00d (patch) | |
| tree | 719980707e5b162d6260a374f611c0aa3718c0aa /src/cpu/inst_seq.hh | |
| parent | 8a690593f4f4980df3fc5f4609674b1e3e62b1bc (diff) | |
| download | gem5-fcec1bf88c0f2e14f3c0c2dd59475757a7a6b00d.tar.xz | |
arch-arm: Correct masking of cp10 and cp11 in CPACR
This patch fixes the masking of cp10 and cp11 in CPACR according to
NSACR.cp10 / NSACR.cp11 by adding the condition "in Non-secure state,
if EL3 is implemented and is using AArch32...", which is specified in
ARM ARM.
Change-Id: Id00e7bf04d6a985e27dbf1028677da0746b79924
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10044
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/inst_seq.hh')
0 files changed, 0 insertions, 0 deletions