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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-05 03:22:34 -0400 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-05 03:22:34 -0400 |
| commit | 706597f021811511e71fddeeab7dcfc33bfd5f35 (patch) | |
| tree | 3967d475572bc0e380ee430eec9035ba35b0d216 /src/cpu/inteltrace.cc | |
| parent | 48281375ee23283d24cf9d7fe5f6315afdb3a6fc (diff) | |
| download | gem5-706597f021811511e71fddeeab7dcfc33bfd5f35.tar.xz | |
arm: Relax ordering for some uncacheable accesses
We currently assume that all uncacheable memory accesses are strictly
ordered. Instead of always enforcing strict ordering, we now only
enforce it if the required memory type is device memory or strongly
ordered memory.
Diffstat (limited to 'src/cpu/inteltrace.cc')
0 files changed, 0 insertions, 0 deletions