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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
| commit | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch) | |
| tree | 874b659c6a5eaa1316cde9eb82ec7d08badf638a /src/cpu/intr_control.cc | |
| parent | e255fa053f8d105de8d188077a318124a3aad9ce (diff) | |
| download | gem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz | |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'src/cpu/intr_control.cc')
| -rw-r--r-- | src/cpu/intr_control.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc index 8f3808889..ca24495f4 100644 --- a/src/cpu/intr_control.cc +++ b/src/cpu/intr_control.cc @@ -51,7 +51,7 @@ IntrControl::post(int cpu_id, int int_num, int index) DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id); std::vector<ThreadContext *> &tcvec = sys->threadContexts; BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); - cpu->postInterrupt(int_num, index); + cpu->postInterrupt(tcvec[cpu_id]->threadId(), int_num, index); } void @@ -60,7 +60,7 @@ IntrControl::clear(int cpu_id, int int_num, int index) DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id); std::vector<ThreadContext *> &tcvec = sys->threadContexts; BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); - cpu->clearInterrupt(int_num, index); + cpu->clearInterrupt(tcvec[cpu_id]->threadId(), int_num, index); } IntrControl * |