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| author | Tushar Krishna <tushar@csail.mit.edu> | 2011-11-04 18:40:22 -0400 |
|---|---|---|
| committer | Tushar Krishna <tushar@csail.mit.edu> | 2011-11-04 18:40:22 -0400 |
| commit | ac993964a93b7d2190aa178dc0d5c1c0ade4a966 (patch) | |
| tree | 292a8fd447690367721ec955ac2b3895d09731df /src/cpu/intr_control.cc | |
| parent | 5ff6e05ffdf926523969de471044c9de8b00d593 (diff) | |
| download | gem5-ac993964a93b7d2190aa178dc0d5c1c0ade4a966.tar.xz | |
GARNET: adding a fault model for resilient on-chip network research.
This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.
Diffstat (limited to 'src/cpu/intr_control.cc')
0 files changed, 0 insertions, 0 deletions