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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-04-22 13:20:32 -0400
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-04-22 13:20:32 -0400
commit33ab8f735d0979ef68d7202d3adbf28f1ae2aceb (patch)
treebebe6fd8140fc9b33c69af7897ed0cb2cc9409cd /src/cpu/kvm/arm_cpu.cc
parent1c529a4196a5f9efcce5c639622d5b55912a472b (diff)
downloadgem5-33ab8f735d0979ef68d7202d3adbf28f1ae2aceb.tar.xz
kvm: Add support for pseudo-ops on ARM
This changeset adds support for m5 pseudo-ops when running in kvm-mode. Unfortunately, we can't trap the normal gem5 co-processor entry in KVM (it doesn't seem to be possible to trap accesses to non-existing co-processors). We therefore use BZJ instructions to cause a trap from virtualized mode into gem5. The BZJ instruction is becomes a normal branch to the gem5 fallback code when running in simulated mode, which means that this patch does not need to change the ARM ISA-specific code. Note: This requires a patched host kernel.
Diffstat (limited to 'src/cpu/kvm/arm_cpu.cc')
-rw-r--r--src/cpu/kvm/arm_cpu.cc21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/cpu/kvm/arm_cpu.cc b/src/cpu/kvm/arm_cpu.cc
index d1082c53e..e131202a4 100644
--- a/src/cpu/kvm/arm_cpu.cc
+++ b/src/cpu/kvm/arm_cpu.cc
@@ -49,6 +49,7 @@
#include "debug/Kvm.hh"
#include "debug/KvmContext.hh"
#include "debug/KvmInt.hh"
+#include "sim/pseudo_inst.hh"
using namespace ArmISA;
@@ -310,6 +311,26 @@ ArmKvmCPU::updateThreadContext()
updateTCStateMisc();
}
+Tick
+ArmKvmCPU::onKvmExitHypercall()
+{
+ ThreadContext *tc(getContext(0));
+ const uint32_t reg_ip(tc->readIntRegFlat(INTREG_R12));
+ const uint8_t func((reg_ip >> 8) & 0xFF);
+ const uint8_t subfunc(reg_ip & 0xFF);
+
+ DPRINTF(Kvm, "KVM Hypercall: 0x%x/0x%x\n", func, subfunc);
+ const uint64_t ret(PseudoInst::pseudoInst(getContext(0), func, subfunc));
+
+ // Just set the return value using the KVM API instead of messing
+ // with the context. We could have used the context, but that
+ // would have required us to request a full context sync.
+ setOneReg(REG_CORE32(usr_regs.ARM_r0), ret & 0xFFFFFFFF);
+ setOneReg(REG_CORE32(usr_regs.ARM_r1), (ret >> 32) & 0xFFFFFFFF);
+
+ return 0;
+}
+
const ArmKvmCPU::RegIndexVector &
ArmKvmCPU::getRegList() const
{