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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
| commit | 8615b27174ae06db4665016c877b1e88031af203 (patch) | |
| tree | 7b28888f71e7e41e84d4087b6ccb53670e04582b /src/cpu/kvm/base.cc | |
| parent | 76ee011a12ade238d5cbf4b570e1d34d7ba72687 (diff) | |
| download | gem5-8615b27174ae06db4665016c877b1e88031af203.tar.xz | |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
Diffstat (limited to 'src/cpu/kvm/base.cc')
| -rw-r--r-- | src/cpu/kvm/base.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc index bf4d68603..0670f61c6 100644 --- a/src/cpu/kvm/base.cc +++ b/src/cpu/kvm/base.cc @@ -1027,7 +1027,7 @@ BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write) syncThreadContext(); Request mmio_req(paddr, size, Request::UNCACHEABLE, dataMasterId()); - mmio_req.setThreadContext(tc->contextId(), 0); + mmio_req.setContext(tc->contextId()); // Some architectures do need to massage physical addresses a bit // before they are inserted into the memory system. This enables // APIC accesses on x86 and m5ops where supported through a MMIO |