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| author | Gabe Black <gabeblack@google.com> | 2018-10-13 00:54:32 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-16 20:27:47 +0000 |
| commit | cf0f625b47a8e0334fc3fe8c0c2cdf5aaaf3389e (patch) | |
| tree | 75505d60b69951ec0a99ca82e8621803c95d921d /src/cpu/kvm/x86_cpu.cc | |
| parent | 0c4515ce1ff2a4e40d243df734af2a67cb8b1ad1 (diff) | |
| download | gem5-cf0f625b47a8e0334fc3fe8c0c2cdf5aaaf3389e.tar.xz | |
cpu: dev: sim: gpu-compute: Banish some ISA specific register types.
These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are
some remaining types, specifically the vector registers and the CCReg.
I'm less familiar with these new types of registers, and so will look
at getting rid of them at some later time.
Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b
Reviewed-on: https://gem5-review.googlesource.com/c/13624
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/kvm/x86_cpu.cc')
| -rw-r--r-- | src/cpu/kvm/x86_cpu.cc | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc index c7625bcc6..268fb9e6d 100644 --- a/src/cpu/kvm/x86_cpu.cc +++ b/src/cpu/kvm/x86_cpu.cc @@ -823,9 +823,6 @@ template <typename T> static void updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) { - static_assert(sizeof(X86ISA::FloatRegBits) == 8, - "Unexpected size of X86ISA::FloatRegBits"); - fpu.mxcsr = tc->readMiscRegNoEffect(MISCREG_MXCSR); fpu.fcw = tc->readMiscRegNoEffect(MISCREG_FCW); // No need to rebuild from MISCREG_FSW and MISCREG_TOP if we read @@ -850,9 +847,9 @@ updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) // TODO: We should update the MMX state for (int i = 0; i < 16; ++i) { - *(X86ISA::FloatRegBits *)&fpu.xmm[i][0] = + *(uint64_t *)&fpu.xmm[i][0] = tc->readFloatRegBits(FLOATREG_XMM_LOW(i)); - *(X86ISA::FloatRegBits *)&fpu.xmm[i][8] = + *(uint64_t *)&fpu.xmm[i][8] = tc->readFloatRegBits(FLOATREG_XMM_HIGH(i)); } } @@ -1048,9 +1045,6 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) { const unsigned top((fpu.fsw >> 11) & 0x7); - static_assert(sizeof(X86ISA::FloatRegBits) == 8, - "Unexpected size of X86ISA::FloatRegBits"); - for (int i = 0; i < 8; ++i) { const unsigned reg_idx((i + top) & 0x7); const double value(X86ISA::loadFloat80(fpu.fpr[i])); @@ -1075,9 +1069,9 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) for (int i = 0; i < 16; ++i) { tc->setFloatRegBits(FLOATREG_XMM_LOW(i), - *(X86ISA::FloatRegBits *)&fpu.xmm[i][0]); + *(uint64_t *)&fpu.xmm[i][0]); tc->setFloatRegBits(FLOATREG_XMM_HIGH(i), - *(X86ISA::FloatRegBits *)&fpu.xmm[i][8]); + *(uint64_t *)&fpu.xmm[i][8]); } } |