diff options
| author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
| commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
| tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/cpu/kvm | |
| parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
| download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz | |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/kvm')
| -rw-r--r-- | src/cpu/kvm/x86_cpu.cc | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc index 268fb9e6d..681e14200 100644 --- a/src/cpu/kvm/x86_cpu.cc +++ b/src/cpu/kvm/x86_cpu.cc @@ -838,7 +838,7 @@ updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) for (int i = 0; i < 8; ++i) { const unsigned reg_idx((i + top) & 0x7); const double value(bitsToFloat64( - tc->readFloatRegBits(FLOATREG_FPR(reg_idx)))); + tc->readFloatReg(FLOATREG_FPR(reg_idx)))); DPRINTF(KvmContext, "Setting KVM FP reg %i (st[%i]) := %f\n", reg_idx, i, value); X86ISA::storeFloat80(fpu.fpr[i], value); @@ -848,9 +848,9 @@ updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) for (int i = 0; i < 16; ++i) { *(uint64_t *)&fpu.xmm[i][0] = - tc->readFloatRegBits(FLOATREG_XMM_LOW(i)); + tc->readFloatReg(FLOATREG_XMM_LOW(i)); *(uint64_t *)&fpu.xmm[i][8] = - tc->readFloatRegBits(FLOATREG_XMM_HIGH(i)); + tc->readFloatReg(FLOATREG_XMM_HIGH(i)); } } @@ -1050,7 +1050,7 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) const double value(X86ISA::loadFloat80(fpu.fpr[i])); DPRINTF(KvmContext, "Setting gem5 FP reg %i (st[%i]) := %f\n", reg_idx, i, value); - tc->setFloatRegBits(FLOATREG_FPR(reg_idx), floatToBits64(value)); + tc->setFloatReg(FLOATREG_FPR(reg_idx), floatToBits64(value)); } // TODO: We should update the MMX state @@ -1068,10 +1068,8 @@ updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) tc->setMiscRegNoEffect(MISCREG_FOP, fpu.last_opcode); for (int i = 0; i < 16; ++i) { - tc->setFloatRegBits(FLOATREG_XMM_LOW(i), - *(uint64_t *)&fpu.xmm[i][0]); - tc->setFloatRegBits(FLOATREG_XMM_HIGH(i), - *(uint64_t *)&fpu.xmm[i][8]); + tc->setFloatReg(FLOATREG_XMM_LOW(i), *(uint64_t *)&fpu.xmm[i][0]); + tc->setFloatReg(FLOATREG_XMM_HIGH(i), *(uint64_t *)&fpu.xmm[i][8]); } } |