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| author | Gabe Black <gabeblack@google.com> | 2019-09-02 21:26:12 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-19 01:45:48 +0000 |
| commit | ae390c629f2a10fd6a1c2eb50b7d3510d6e091da (patch) | |
| tree | 51f12635838755ef7519bea1c72bfb96e0214336 /src/cpu/kvm | |
| parent | 1c047f8b92f5708bbef50d24cf47902d5da313e3 (diff) | |
| download | gem5-ae390c629f2a10fd6a1c2eb50b7d3510d6e091da.tar.xz | |
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/kvm')
| -rw-r--r-- | src/cpu/kvm/base.hh | 1 | ||||
| -rw-r--r-- | src/cpu/kvm/x86_cpu.cc | 10 |
2 files changed, 8 insertions, 3 deletions
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh index 7bf518f04..8d1258b4c 100644 --- a/src/cpu/kvm/base.hh +++ b/src/cpu/kvm/base.hh @@ -52,6 +52,7 @@ #include "cpu/kvm/vm.hh" #include "cpu/base.hh" #include "cpu/simple_thread.hh" +#include "sim/faults.hh" /** Signal to use to trigger exits from KVM */ #define KVM_KICK_SIGNAL SIGRTMIN diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc index 681e14200..5d2250dae 100644 --- a/src/cpu/kvm/x86_cpu.cc +++ b/src/cpu/kvm/x86_cpu.cc @@ -38,6 +38,8 @@ #include "arch/registers.hh" #include "arch/x86/cpuid.hh" +#include "arch/x86/faults.hh" +#include "arch/x86/interrupts.hh" #include "arch/x86/regs/msr.hh" #include "arch/x86/utility.hh" #include "cpu/kvm/base.hh" @@ -1185,8 +1187,10 @@ X86KvmCPU::kvmRun(Tick ticks) { struct kvm_run &kvm_run(*getKvmRunState()); - if (interrupts[0]->checkInterruptsRaw()) { - if (interrupts[0]->hasPendingUnmaskable()) { + auto *lapic = dynamic_cast<X86ISA::Interrupts *>(interrupts[0]); + + if (lapic->checkInterruptsRaw()) { + if (lapic->hasPendingUnmaskable()) { DPRINTF(KvmInt, "Delivering unmaskable interrupt.\n"); syncThreadContext(); @@ -1198,7 +1202,7 @@ X86KvmCPU::kvmRun(Tick ticks) // the thread context and check if there are /really/ // interrupts that should be delivered now. syncThreadContext(); - if (interrupts[0]->checkInterrupts(tc)) { + if (lapic->checkInterrupts(tc)) { DPRINTF(KvmInt, "M5 has pending interrupts, delivering interrupt.\n"); |