More cache fixes. Atomic coherence now works as well.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
    Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
    Debug output.
    Clean up memleak in atomic mode.
    Set hitLatency.
    Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
    Add command strings for new commands
src/python/m5/objects/MemTest.py:
    Add param to test atomic memory.

--HG--
extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b

1 files changed, 28 insertions, 13 deletions

diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 127cad414..f42f0f8e2 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -72,6 +72,9 @@ void
 MemTest::CpuPort::recvFunctional(Packet *pkt)
 {
     //Do nothing if we see one come through
+    if (curTick != 0)//Supress warning durring initialization
+        warn("Functional Writes not implemented in MemTester\n");
+    //Need to find any response values that intersect and update
     return;
 }
 
@@ -90,6 +93,20 @@ MemTest::CpuPort::recvRetry()
     memtest->doRetry();
 }
 
+void
+MemTest::sendPkt(Packet *pkt) {
+    if (atomic) {
+        cachePort.sendAtomic(pkt);
+        pkt->makeAtomicResponse();
+        completeRequest(pkt);
+    }
+    else if (!cachePort.sendTiming(pkt)) {
+        accessRetry = true;
+        retryPkt = pkt;
+    }
+
+}
+
 MemTest::MemTest(const string &name,
 //		 MemInterface *_cache_interface,
 //		 PhysicalMemory *main_mem,
@@ -102,7 +119,8 @@ MemTest::MemTest(const string &name,
                  unsigned _percentSourceUnaligned,
                  unsigned _percentDestUnaligned,
                  Addr _traceAddr,
-                 Counter _max_loads)
+                 Counter _max_loads,
+                 bool _atomic)
     : MemObject(name),
       tickEvent(this),
       cachePort("test", this),
@@ -118,7 +136,8 @@ MemTest::MemTest(const string &name,
       nextProgressMessage(_progressInterval),
       percentSourceUnaligned(_percentSourceUnaligned),
       percentDestUnaligned(percentDestUnaligned),
-      maxLoads(_max_loads)
+      maxLoads(_max_loads),
+      atomic(_atomic)
 {
     vector<string> cmd;
     cmd.push_back("/bin/ls");
@@ -368,10 +387,7 @@ MemTest::tick()
             completeRequest(pkt);
         } else {
 //	    req->completionEvent = new MemCompleteEvent(req, result, this);
-            if (!cachePort.sendTiming(pkt)) {
-                accessRetry = true;
-                retryPkt = pkt;
-            }
+            sendPkt(pkt);
         }
     } else {
         // write
@@ -406,13 +422,10 @@ MemTest::tick()
 
         if (probe) {
             cachePort.sendFunctional(pkt);
-//	    completeRequest(req, NULL);
+            completeRequest(pkt);
         } else {
 //	    req->completionEvent = new MemCompleteEvent(req, NULL, this);
-            if (!cachePort.sendTiming(pkt)) {
-                accessRetry = true;
-                retryPkt = pkt;
-            }
+            sendPkt(pkt);
         }
     }
 /*    else {
@@ -484,6 +497,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
     Param<unsigned> percent_dest_unaligned;
     Param<Addr> trace_addr;
     Param<Counter> max_loads;
+    Param<bool> atomic;
 
 END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 
@@ -503,7 +517,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
     INIT_PARAM(percent_dest_unaligned,
                "percent of copy dest address that are unaligned"),
     INIT_PARAM(trace_addr, "address to trace"),
-    INIT_PARAM(max_loads, "terminate when we have reached this load count")
+                              INIT_PARAM(max_loads, "terminate when we have reached this load count"),
+    INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
 
 END_INIT_SIM_OBJECT_PARAMS(MemTest)
 
@@ -514,7 +529,7 @@ CREATE_SIM_OBJECT(MemTest)
                        /*check_mem,*/ memory_size, percent_reads, /*percent_copies,*/
                        percent_uncacheable, progress_interval,
                        percent_source_unaligned, percent_dest_unaligned,
-                       trace_addr, max_loads);
+                       trace_addr, max_loads, atomic);
 }
 
 REGISTER_SIM_OBJECT("MemTest", MemTest)