Merge zizzer.eecs.umich.edu:/bk/newmem

into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a

1 files changed, 224 insertions, 132 deletions

diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 7ea9eaefc..f42f0f8e2 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -38,86 +38,158 @@
 
 #include "base/misc.hh"
 #include "base/statistics.hh"
-#include "cpu/simple_thread.hh"
+//#include "cpu/simple_thread.hh"
 #include "cpu/memtest/memtest.hh"
-#include "mem/cache/base_cache.hh"
+//#include "mem/cache/base_cache.hh"
+//#include "mem/physical.hh"
 #include "sim/builder.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+#include "mem/port.hh"
+#include "mem/mem_object.hh"
 
 using namespace std;
-using namespace TheISA;
 
 int TESTER_ALLOCATOR=0;
 
+bool
+MemTest::CpuPort::recvTiming(Packet *pkt)
+{
+    memtest->completeRequest(pkt);
+    return true;
+}
+
+Tick
+MemTest::CpuPort::recvAtomic(Packet *pkt)
+{
+    panic("MemTest doesn't expect recvAtomic callback!");
+    return curTick;
+}
+
+void
+MemTest::CpuPort::recvFunctional(Packet *pkt)
+{
+    //Do nothing if we see one come through
+    if (curTick != 0)//Supress warning durring initialization
+        warn("Functional Writes not implemented in MemTester\n");
+    //Need to find any response values that intersect and update
+    return;
+}
+
+void
+MemTest::CpuPort::recvStatusChange(Status status)
+{
+    if (status == RangeChange)
+        return;
+
+    panic("MemTest doesn't expect recvStatusChange callback!");
+}
+
+void
+MemTest::CpuPort::recvRetry()
+{
+    memtest->doRetry();
+}
+
+void
+MemTest::sendPkt(Packet *pkt) {
+    if (atomic) {
+        cachePort.sendAtomic(pkt);
+        pkt->makeAtomicResponse();
+        completeRequest(pkt);
+    }
+    else if (!cachePort.sendTiming(pkt)) {
+        accessRetry = true;
+        retryPkt = pkt;
+    }
+
+}
+
 MemTest::MemTest(const string &name,
-                 MemInterface *_cache_interface,
-                 FunctionalMemory *main_mem,
-                 FunctionalMemory *check_mem,
+//		 MemInterface *_cache_interface,
+//		 PhysicalMemory *main_mem,
+//		 PhysicalMemory *check_mem,
                  unsigned _memorySize,
                  unsigned _percentReads,
-                 unsigned _percentCopies,
+//		 unsigned _percentCopies,
                  unsigned _percentUncacheable,
                  unsigned _progressInterval,
                  unsigned _percentSourceUnaligned,
                  unsigned _percentDestUnaligned,
                  Addr _traceAddr,
-                 Counter _max_loads)
-    : SimObject(name),
+                 Counter _max_loads,
+                 bool _atomic)
+    : MemObject(name),
       tickEvent(this),
-      cacheInterface(_cache_interface),
-      mainMem(main_mem),
-      checkMem(check_mem),
+      cachePort("test", this),
+      funcPort("functional", this),
+      retryPkt(NULL),
+//      mainMem(main_mem),
+//      checkMem(check_mem),
       size(_memorySize),
       percentReads(_percentReads),
-      percentCopies(_percentCopies),
+//      percentCopies(_percentCopies),
       percentUncacheable(_percentUncacheable),
       progressInterval(_progressInterval),
       nextProgressMessage(_progressInterval),
       percentSourceUnaligned(_percentSourceUnaligned),
       percentDestUnaligned(percentDestUnaligned),
-      maxLoads(_max_loads)
+      maxLoads(_max_loads),
+      atomic(_atomic)
 {
     vector<string> cmd;
     cmd.push_back("/bin/ls");
     vector<string> null_vec;
-    thread = new SimpleThread(NULL, 0, mainMem, 0);
-
-    blockSize = cacheInterface->getBlockSize();
-    blockAddrMask = blockSize - 1;
-    traceBlockAddr = blockAddr(_traceAddr);
-
-    //setup data storage with interesting values
-    uint8_t *data1 = new uint8_t[size];
-    uint8_t *data2 = new uint8_t[size];
-    uint8_t *data3 = new uint8_t[size];
-    memset(data1, 1, size);
-    memset(data2, 2, size);
-    memset(data3, 3, size);
+    //  thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
     curTick = 0;
 
+    // Needs to be masked off once we know the block size.
+    traceBlockAddr = _traceAddr;
     baseAddr1 = 0x100000;
     baseAddr2 = 0x400000;
     uncacheAddr = 0x800000;
 
-    // set up intial memory contents here
-    mainMem->prot_write(baseAddr1, data1, size);
-    checkMem->prot_write(baseAddr1, data1, size);
-    mainMem->prot_write(baseAddr2, data2, size);
-    checkMem->prot_write(baseAddr2, data2, size);
-    mainMem->prot_write(uncacheAddr, data3, size);
-    checkMem->prot_write(uncacheAddr, data3, size);
-
-    delete [] data1;
-    delete [] data2;
-    delete [] data3;
-
     // set up counters
     noResponseCycles = 0;
     numReads = 0;
     tickEvent.schedule(0);
 
     id = TESTER_ALLOCATOR++;
+    if (TESTER_ALLOCATOR > 8)
+        panic("False sharing memtester only allows up to 8 testers");
+
+    accessRetry = false;
+}
+
+Port *
+MemTest::getPort(const std::string &if_name, int idx)
+{
+    if (if_name == "functional")
+        return &funcPort;
+    else if (if_name == "test")
+        return &cachePort;
+    else
+        panic("No Such Port\n");
+}
+
+void
+MemTest::init()
+{
+    // By the time init() is called, the ports should be hooked up.
+    blockSize = cachePort.peerBlockSize();
+    blockAddrMask = blockSize - 1;
+    traceBlockAddr = blockAddr(traceBlockAddr);
+
+    // set up intial memory contents here
+
+    cachePort.memsetBlob(baseAddr1, 1, size);
+    funcPort.memsetBlob(baseAddr1, 1, size);
+    cachePort.memsetBlob(baseAddr2, 2, size);
+    funcPort.memsetBlob(baseAddr2, 2, size);
+    cachePort.memsetBlob(uncacheAddr, 3, size);
+    funcPort.memsetBlob(uncacheAddr, 3, size);
 }
 
 static void
@@ -132,23 +204,31 @@ printData(ostream &os, uint8_t *data, int nbytes)
 }
 
 void
-MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
+MemTest::completeRequest(Packet *pkt)
 {
+    MemTestSenderState *state =
+        dynamic_cast<MemTestSenderState *>(pkt->senderState);
+
+    uint8_t *data = state->data;
+    uint8_t *pkt_data = pkt->getPtr<uint8_t>();
+    Request *req = pkt->req;
+
     //Remove the address from the list of outstanding
-    std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->paddr);
+    std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr());
     assert(removeAddr != outstandingAddrs.end());
     outstandingAddrs.erase(removeAddr);
 
-    switch (req->cmd) {
-      case Read:
-        if (memcmp(req->data, data, req->size) != 0) {
-            cerr << name() << ": on read of 0x" << hex << req->paddr
-                 << " (0x" << hex << blockAddr(req->paddr) << ")"
+    switch (pkt->cmd) {
+      case Packet::ReadResp:
+
+        if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
+            cerr << name() << ": on read of 0x" << hex << req->getPaddr()
+                 << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
                  << "@ cycle " << dec << curTick
                  << ", cache returns 0x";
-            printData(cerr, req->data, req->size);
+            printData(cerr, pkt_data, pkt->getSize());
             cerr << ", expected 0x";
-            printData(cerr, data, req->size);
+            printData(cerr, data, pkt->getSize());
             cerr << endl;
             fatal("");
         }
@@ -163,13 +243,13 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
         }
 
         if (numReads >= maxLoads)
-            SimExit(curTick, "Maximum number of loads reached!");
+            exitSimLoop("Maximum number of loads reached!");
         break;
 
-      case Write:
+      case Packet::WriteResp:
         numWritesStat++;
         break;
-
+/*
       case Copy:
         //Also remove dest from outstanding list
         removeAddr = outstandingAddrs.find(req->dest);
@@ -177,36 +257,37 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
         outstandingAddrs.erase(removeAddr);
         numCopiesStat++;
         break;
-
+*/
       default:
         panic("invalid command");
     }
 
-    if (blockAddr(req->paddr) == traceBlockAddr) {
+    if (blockAddr(req->getPaddr()) == traceBlockAddr) {
         cerr << name() << ": completed "
-             << (req->cmd.isWrite() ? "write" : "read")
+             << (pkt->isWrite() ? "write" : "read")
              << " access of "
-             << dec << req->size << " bytes at address 0x"
-             << hex << req->paddr
-             << " (0x" << hex << blockAddr(req->paddr) << ")"
+             << dec << pkt->getSize() << " bytes at address 0x"
+             << hex << req->getPaddr()
+             << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
              << ", value = 0x";
-        printData(cerr, req->data, req->size);
+        printData(cerr, pkt_data, pkt->getSize());
         cerr << " @ cycle " << dec << curTick;
 
         cerr << endl;
     }
 
     noResponseCycles = 0;
+    delete state;
     delete [] data;
+    delete pkt->req;
+    delete pkt;
 }
 
-
 void
 MemTest::regStats()
 {
     using namespace Stats;
 
-
     numReadsStat
         .name(name() + ".num_reads")
         .desc("number of read accesses completed")
@@ -234,7 +315,7 @@ MemTest::tick()
         fatal("");
     }
 
-    if (cacheInterface->isBlocked()) {
+    if (accessRetry) {
         return;
     }
 
@@ -248,30 +329,30 @@ MemTest::tick()
 
     //If we aren't doing copies, use id as offset, and do a false sharing
     //mem tester
-    if (percentCopies == 0) {
-        //We can eliminate the lower bits of the offset, and then use the id
-        //to offset within the blks
-        offset &= ~63; //Not the low order bits
-        offset += id;
-        access_size = 0;
-    }
+    //We can eliminate the lower bits of the offset, and then use the id
+    //to offset within the blks
+    offset &= ~63; //Not the low order bits
+    offset += id;
+    access_size = 0;
 
-    MemReqPtr req = new MemReq();
+    Request *req = new Request();
+    uint32_t flags = 0;
+    Addr paddr;
 
     if (cacheable < percentUncacheable) {
-        req->flags |= UNCACHEABLE;
-        req->paddr = uncacheAddr + offset;
+        flags |= UNCACHEABLE;
+        paddr = uncacheAddr + offset;
     } else {
-        req->paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
+        paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
     }
-    // bool probe = (random() % 2 == 1) && !req->isUncacheable();
+    //bool probe = (random() % 2 == 1) && !req->isUncacheable();
     bool probe = false;
 
-    req->size = 1 << access_size;
-    req->data = new uint8_t[req->size];
-    req->paddr &= ~(req->size - 1);
-    req->time = curTick;
-    req->xc = thread->getProxy();
+    paddr &= ~((1 << access_size) - 1);
+    req->setPhys(paddr, 1 << access_size, flags);
+    req->setThreadContext(id,0);
+
+    uint8_t *result = new uint8_t[8];
 
     if (cmd < percentReads) {
         // read
@@ -279,60 +360,75 @@ MemTest::tick()
         //For now we only allow one outstanding request per addreess per tester
         //This means we assume CPU does write forwarding to reads that alias something
         //in the cpu store buffer.
-        if (outstandingAddrs.find(req->paddr) != outstandingAddrs.end()) return;
-        else outstandingAddrs.insert(req->paddr);
+        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
+        else outstandingAddrs.insert(paddr);
+
+        // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
+        funcPort.readBlob(req->getPaddr(), result, req->getSize());
 
-        req->cmd = Read;
-        uint8_t *result = new uint8_t[8];
-        checkMem->access(Read, req->paddr, result, req->size);
-        if (blockAddr(req->paddr) == traceBlockAddr) {
+        if (blockAddr(paddr) == traceBlockAddr) {
             cerr << name()
                  << ": initiating read "
                  << ((probe) ? "probe of " : "access of ")
-                 << dec << req->size << " bytes from addr 0x"
-                 << hex << req->paddr
-                 << " (0x" << hex << blockAddr(req->paddr) << ")"
+                 << dec << req->getSize() << " bytes from addr 0x"
+                 << hex << paddr
+                 << " (0x" << hex << blockAddr(paddr) << ")"
                  << " at cycle "
                  << dec << curTick << endl;
         }
+
+        Packet *pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+        pkt->dataDynamicArray(new uint8_t[req->getSize()]);
+        MemTestSenderState *state = new MemTestSenderState(result);
+        pkt->senderState = state;
+
         if (probe) {
-            cacheInterface->probeAndUpdate(req);
-            completeRequest(req, result);
+            cachePort.sendFunctional(pkt);
+            completeRequest(pkt);
         } else {
-            req->completionEvent = new MemCompleteEvent(req, result, this);
-            cacheInterface->access(req);
+//	    req->completionEvent = new MemCompleteEvent(req, result, this);
+            sendPkt(pkt);
         }
-    } else if (cmd < (100 - percentCopies)){
+    } else {
         // write
 
         //For now we only allow one outstanding request per addreess per tester
         //This means we assume CPU does write forwarding to reads that alias something
         //in the cpu store buffer.
-        if (outstandingAddrs.find(req->paddr) != outstandingAddrs.end()) return;
-        else outstandingAddrs.insert(req->paddr);
+        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return;
+        else outstandingAddrs.insert(paddr);
 
-        req->cmd = Write;
-        memcpy(req->data, &data, req->size);
-        checkMem->access(Write, req->paddr, req->data, req->size);
-        if (blockAddr(req->paddr) == traceBlockAddr) {
+/*
+        if (blockAddr(req->getPaddr()) == traceBlockAddr) {
             cerr << name() << ": initiating write "
                  << ((probe)?"probe of ":"access of ")
-                 << dec << req->size << " bytes (value = 0x";
-            printData(cerr, req->data, req->size);
+                 << dec << req->getSize() << " bytes (value = 0x";
+            printData(cerr, data_pkt->getPtr(), req->getSize());
             cerr << ") to addr 0x"
-                 << hex << req->paddr
-                 << " (0x" << hex << blockAddr(req->paddr) << ")"
+                 << hex << req->getPaddr()
+                 << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
                  << " at cycle "
                  << dec << curTick << endl;
         }
+*/
+        Packet *pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+        uint8_t *pkt_data = new uint8_t[req->getSize()];
+        pkt->dataDynamicArray(pkt_data);
+        memcpy(pkt_data, &data, req->getSize());
+        MemTestSenderState *state = new MemTestSenderState(result);
+        pkt->senderState = state;
+
+        funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
+
         if (probe) {
-            cacheInterface->probeAndUpdate(req);
-            completeRequest(req, NULL);
+            cachePort.sendFunctional(pkt);
+            completeRequest(pkt);
         } else {
-            req->completionEvent = new MemCompleteEvent(req, NULL, this);
-            cacheInterface->access(req);
+//	    req->completionEvent = new MemCompleteEvent(req, NULL, this);
+            sendPkt(pkt);
         }
-    } else {
+    }
+/*    else {
         // copy
         unsigned source_align = random() % 100;
         unsigned dest_align = random() % 100;
@@ -369,56 +465,51 @@ MemTest::tick()
                  << " (0x" << hex << blockAddr(dest) << ")"
                  << " at cycle "
                  << dec << curTick << endl;
-        }
+        }*
         cacheInterface->access(req);
         uint8_t result[blockSize];
         checkMem->access(Read, source, &result, blockSize);
         checkMem->access(Write, dest, &result, blockSize);
     }
+*/
 }
 
-
 void
-MemCompleteEvent::process()
-{
-    tester->completeRequest(req, data);
-    delete this;
-}
-
-
-const char *
-MemCompleteEvent::description()
+MemTest::doRetry()
 {
-    return "memory access completion";
+    if (cachePort.sendTiming(retryPkt)) {
+        accessRetry = false;
+        retryPkt = NULL;
+    }
 }
 
-
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 
-    SimObjectParam<BaseCache *> cache;
-    SimObjectParam<FunctionalMemory *> main_mem;
-    SimObjectParam<FunctionalMemory *> check_mem;
+//    SimObjectParam<BaseCache *> cache;
+//    SimObjectParam<PhysicalMemory *> main_mem;
+//    SimObjectParam<PhysicalMemory *> check_mem;
     Param<unsigned> memory_size;
     Param<unsigned> percent_reads;
-    Param<unsigned> percent_copies;
+//    Param<unsigned> percent_copies;
     Param<unsigned> percent_uncacheable;
     Param<unsigned> progress_interval;
     Param<unsigned> percent_source_unaligned;
     Param<unsigned> percent_dest_unaligned;
     Param<Addr> trace_addr;
     Param<Counter> max_loads;
+    Param<bool> atomic;
 
 END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
 
-    INIT_PARAM(cache, "L1 cache"),
-    INIT_PARAM(main_mem, "hierarchical memory"),
-    INIT_PARAM(check_mem, "check memory"),
+//    INIT_PARAM(cache, "L1 cache"),
+//    INIT_PARAM(main_mem, "hierarchical memory"),
+//    INIT_PARAM(check_mem, "check memory"),
     INIT_PARAM(memory_size, "memory size"),
     INIT_PARAM(percent_reads, "target read percentage"),
-    INIT_PARAM(percent_copies, "target copy percentage"),
+//    INIT_PARAM(percent_copies, "target copy percentage"),
     INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
     INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
     INIT_PARAM(percent_source_unaligned,
@@ -426,18 +517,19 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
     INIT_PARAM(percent_dest_unaligned,
                "percent of copy dest address that are unaligned"),
     INIT_PARAM(trace_addr, "address to trace"),
-    INIT_PARAM(max_loads, "terminate when we have reached this load count")
+                              INIT_PARAM(max_loads, "terminate when we have reached this load count"),
+    INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
 
 END_INIT_SIM_OBJECT_PARAMS(MemTest)
 
 
 CREATE_SIM_OBJECT(MemTest)
 {
-    return new MemTest(getInstanceName(), cache->getInterface(), main_mem,
-                       check_mem, memory_size, percent_reads, percent_copies,
+    return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
+                       /*check_mem,*/ memory_size, percent_reads, /*percent_copies,*/
                        percent_uncacheable, progress_interval,
                        percent_source_unaligned, percent_dest_unaligned,
-                       trace_addr, max_loads);
+                       trace_addr, max_loads, atomic);
 }
 
 REGISTER_SIM_OBJECT("MemTest", MemTest)