Merge vm1.(none):/home/stever/bk/newmem-head

into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : fba7efd444e1ca9738385dd4662a33feab357e79

2 files changed, 54 insertions, 0 deletions

diff --git a/src/cpu/memtest/MemTest.py b/src/cpu/memtest/MemTest.py
new file mode 100644
index 000000000..381519972
--- /dev/null
+++ b/src/cpu/memtest/MemTest.py
@@ -0,0 +1,52 @@
+# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+
+class MemTest(SimObject):
+    type = 'MemTest'
+    max_loads = Param.Counter("number of loads to execute")
+    atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
+    memory_size = Param.Int(65536, "memory size")
+    percent_dest_unaligned = Param.Percent(50,
+        "percent of copy dest address that are unaligned")
+    percent_reads = Param.Percent(65, "target read percentage")
+    percent_source_unaligned = Param.Percent(50,
+        "percent of copy source address that are unaligned")
+    percent_functional = Param.Percent(50, "percent of access that are functional")
+    percent_uncacheable = Param.Percent(10,
+        "target uncacheable percentage")
+    progress_interval = Param.Counter(1000000,
+        "progress report interval (in accesses)")
+    trace_addr = Param.Addr(0, "address to trace")
+
+    test = Port("Port to the memory system to test")
+    functional = Port("Port to the functional memory used for verification")
diff --git a/src/cpu/memtest/SConscript b/src/cpu/memtest/SConscript
index 7b4d6d2c5..1f6621a4c 100644
--- a/src/cpu/memtest/SConscript
+++ b/src/cpu/memtest/SConscript
@@ -31,4 +31,6 @@
 Import('*')
 
 if 'O3CPU' in env['CPU_MODELS']:
+    SimObject('MemTest.py')
+
     Source('memtest.cc')