diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-10-31 01:21:54 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-10-31 01:21:54 -0400 |
| commit | 538fae951b3a594814dff6bb6d038c32caadb25c (patch) | |
| tree | a74245aab941fe20309c108d2e837e68ea5e4582 /src/cpu/memtest | |
| parent | 8ce31ea471eebb06efa590fb060804aa1fb5266b (diff) | |
| download | gem5-538fae951b3a594814dff6bb6d038c32caadb25c.tar.xz | |
Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
Diffstat (limited to 'src/cpu/memtest')
| -rw-r--r-- | src/cpu/memtest/SConscript | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/memtest/SConscript b/src/cpu/memtest/SConscript index 1f6621a4c..7832632e4 100644 --- a/src/cpu/memtest/SConscript +++ b/src/cpu/memtest/SConscript @@ -34,3 +34,5 @@ if 'O3CPU' in env['CPU_MODELS']: SimObject('MemTest.py') Source('memtest.cc') + + TraceFlag('MemTest') |