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authorSteve Reinhardt <stever@gmail.com>2008-01-02 15:22:38 -0800
committerSteve Reinhardt <stever@gmail.com>2008-01-02 15:22:38 -0800
commit6c5a3ab8b28ae14e1f1c37076b7370b37c70de62 (patch)
treed89626ebae1a7b4a14f41fe6b33d01dbcb78bdc2 /src/cpu/memtest
parentbf9b3821bda5f534a44b176c0ed738a17cb9b80a (diff)
downloadgem5-6c5a3ab8b28ae14e1f1c37076b7370b37c70de62.tar.xz
Add ReadRespWithInvalidate to handle multi-level coherence situation
where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. --HG-- extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
Diffstat (limited to 'src/cpu/memtest')
-rw-r--r--src/cpu/memtest/memtest.cc13
1 files changed, 4 insertions, 9 deletions
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 29da517b3..819b95e70 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -207,9 +207,9 @@ MemTest::completeRequest(PacketPtr pkt)
assert(removeAddr != outstandingAddrs.end());
outstandingAddrs.erase(removeAddr);
- switch (pkt->cmd.toInt()) {
- case MemCmd::ReadResp:
+ assert(pkt->isResponse());
+ if (pkt->isRead()) {
if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
panic("%s: read of %x (blk %x) @ cycle %d "
"returns %x, expected %x\n", name(),
@@ -228,14 +228,9 @@ MemTest::completeRequest(PacketPtr pkt)
if (maxLoads != 0 && numReads >= maxLoads)
exitSimLoop("maximum number of loads reached");
- break;
-
- case MemCmd::WriteResp:
+ } else {
+ assert(pkt->isWrite());
numWritesStat++;
- break;
-
- default:
- panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt());
}
noResponseCycles = 0;