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authorNathan Binkert <nate@binkert.org>2007-07-23 21:51:38 -0700
committerNathan Binkert <nate@binkert.org>2007-07-23 21:51:38 -0700
commitabc76f20cb98c90e8dab416dd16dfd4a954013ba (patch)
treef3131e68a09c1b4537e17df5b14df21df53746e4 /src/cpu/memtest
parent552097b92e37fb4c0fd27960afe0a03c02894f11 (diff)
downloadgem5-abc76f20cb98c90e8dab416dd16dfd4a954013ba.tar.xz
Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
Diffstat (limited to 'src/cpu/memtest')
-rw-r--r--src/cpu/memtest/memtest.cc54
1 files changed, 8 insertions, 46 deletions
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 15774904a..23e2297fe 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -46,7 +46,7 @@
#include "mem/packet.hh"
//#include "mem/physical.hh"
#include "mem/request.hh"
-#include "sim/builder.hh"
+#include "params/MemTest.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
@@ -496,53 +496,15 @@ MemTest::doRetry()
}
}
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-// SimObjectParam<BaseCache *> cache;
-// SimObjectParam<PhysicalMemory *> main_mem;
-// SimObjectParam<PhysicalMemory *> check_mem;
- Param<unsigned> memory_size;
- Param<unsigned> percent_reads;
- Param<unsigned> percent_functional;
- Param<unsigned> percent_uncacheable;
- Param<unsigned> progress_interval;
- Param<unsigned> percent_source_unaligned;
- Param<unsigned> percent_dest_unaligned;
- Param<Addr> trace_addr;
- Param<Counter> max_loads;
- Param<bool> atomic;
-
-END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-// INIT_PARAM(cache, "L1 cache"),
-// INIT_PARAM(main_mem, "hierarchical memory"),
-// INIT_PARAM(check_mem, "check memory"),
- INIT_PARAM(memory_size, "memory size"),
- INIT_PARAM(percent_reads, "target read percentage"),
- INIT_PARAM(percent_functional, "percentage of access that are functional"),
- INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
- INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
- INIT_PARAM(percent_source_unaligned,
- "percent of copy source address that are unaligned"),
- INIT_PARAM(percent_dest_unaligned,
- "percent of copy dest address that are unaligned"),
- INIT_PARAM(trace_addr, "address to trace"),
- INIT_PARAM(max_loads, "terminate when we have reached this load count"),
- INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
-
-END_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-
-CREATE_SIM_OBJECT(MemTest)
+MemTest *
+MemTestParams::create()
{
- return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
- /*check_mem,*/ memory_size, percent_reads, percent_functional,
+ return new MemTest(name,
+#if 0
+ cache->getInterface(), main_mem, check_mem,
+#endif
+ memory_size, percent_reads, percent_functional,
percent_uncacheable, progress_interval,
percent_source_unaligned, percent_dest_unaligned,
trace_addr, max_loads, atomic);
}
-
-REGISTER_SIM_OBJECT("MemTest", MemTest)