diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
commit | 608641e23c7f2288810c3f23a1a63790b664f2ab (patch) | |
tree | 0656aaf9653e8d263f5daac0d5f0fe3190193ae5 /src/cpu/minor/exec_context.hh | |
parent | 6e354e82d9395b20f5f148cd545d0666b626e8ac (diff) | |
download | gem5-608641e23c7f2288810c3f23a1a63790b664f2ab.tar.xz |
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.
Diffstat (limited to 'src/cpu/minor/exec_context.hh')
-rw-r--r-- | src/cpu/minor/exec_context.hh | 43 |
1 files changed, 29 insertions, 14 deletions
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh index 80d5d9872..6ea74047c 100644 --- a/src/cpu/minor/exec_context.hh +++ b/src/cpu/minor/exec_context.hh @@ -140,6 +140,20 @@ class ExecContext : public ::ExecContext return thread.readFloatRegBits(reg_idx); } + TheISA::CCReg + readCCRegOperand(const StaticInst *si, int idx) + { + int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; + return thread.readCCReg(reg_idx); + } + + const TheISA::VectorReg & + readVectorRegOperand(const StaticInst *si, int idx) + { + int reg_idx = si->srcRegIdx(idx) - TheISA::Vector_Reg_Base; + return thread.readVectorReg(reg_idx); + } + void setIntRegOperand(const StaticInst *si, int idx, IntReg val) { @@ -162,6 +176,21 @@ class ExecContext : public ::ExecContext thread.setFloatRegBits(reg_idx, val); } + void + setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) + { + int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; + thread.setCCReg(reg_idx, val); + } + + void + setVectorRegOperand(const StaticInst *si, int idx, + const TheISA::VectorReg &val) + { + int reg_idx = si->destRegIdx(idx) - TheISA::Vector_Reg_Base; + thread.setVectorReg(reg_idx, val); + } + bool readPredicate() { @@ -265,20 +294,6 @@ class ExecContext : public ::ExecContext thread.getDTBPtr()->demapPage(vaddr, asn); } - TheISA::CCReg - readCCRegOperand(const StaticInst *si, int idx) - { - int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; - return thread.readCCReg(reg_idx); - } - - void - setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) - { - int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; - thread.setCCReg(reg_idx, val); - } - void demapInstPage(Addr vaddr, uint64_t asn) { |