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| author | Tuan Ta <qtt2@cornell.edu> | 2019-02-05 10:08:10 -0500 |
|---|---|---|
| committer | Tuan Ta <qtt2@cornell.edu> | 2019-02-06 16:57:48 +0000 |
| commit | 8efcc0faac252d716704b5f8f9f3e1c165910ebe (patch) | |
| tree | 7321e09d0b6399b0147dcb15405d02858eaf30d9 /src/cpu/minor/fetch2.hh | |
| parent | ff5ad434d95403005cbf229a0f4b077b6dbc502b (diff) | |
| download | gem5-8efcc0faac252d716704b5f8f9f3e1c165910ebe.tar.xz | |
arch-riscv: Initialize interrupt mask
This patch initializes RISCV interrupt mask to 0.
Change-Id: I56289d9f3f319e239e305befea006a0ad4d86b75
Reviewed-on: https://gem5-review.googlesource.com/c/16162
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/minor/fetch2.hh')
0 files changed, 0 insertions, 0 deletions