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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-07 11:35:48 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
| commit | 099cb037e83d1e7bb47ec0e8eaf649a63f889d38 (patch) | |
| tree | da6877f00070e243cb83c233fb5debfdf82a15e2 /src/cpu/minor/lsq.cc | |
| parent | 3deff78fe40b9aa3d4e3a8571f13f29072efe4e4 (diff) | |
| download | gem5-099cb037e83d1e7bb47ec0e8eaf649a63f889d38.tar.xz | |
cpu: Add support for CMOs in the cpu models
Cache maintenance operations go through the write channel of the
cpu. This changes makes sure that the cpu does not try to fill in the
packet with data.
Change-Id: Ic83205bb1cda7967636d88f15adcb475eb38d158
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5055
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/minor/lsq.cc')
| -rw-r--r-- | src/cpu/minor/lsq.cc | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc index b7d5360ac..cb0611be3 100644 --- a/src/cpu/minor/lsq.cc +++ b/src/cpu/minor/lsq.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014 ARM Limited + * Copyright (c) 2013-2014,2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -679,8 +679,12 @@ LSQ::StoreBuffer::canForwardDataToLoad(LSQRequestPtr request, while (ret == NoAddrRangeCoverage && i != slots.rend()) { LSQRequestPtr slot = *i; + /* Cache maintenance instructions go down via the store path * + * but they carry no data and they shouldn't be considered for + * forwarding */ if (slot->packet && - slot->inst->id.threadId == request->inst->id.threadId) { + slot->inst->id.threadId == request->inst->id.threadId && + !slot->packet->req->isCacheMaintenance()) { AddrRangeCoverage coverage = slot->containsAddrRangeOf(request); if (coverage != NoAddrRangeCoverage) { @@ -1492,7 +1496,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, /* request_data becomes the property of a ...DataRequest (see below) * and destroyed by its destructor */ request_data = new uint8_t[size]; - if (flags & Request::CACHE_BLOCK_ZERO) { + if (flags & Request::STORE_NO_DATA) { /* For cache zeroing, just use zeroed data */ std::memset(request_data, 0, size); } else { @@ -1562,10 +1566,13 @@ makePacketForRequest(Request &request, bool isLoad, if (sender_state) ret->pushSenderState(sender_state); - if (isLoad) + if (isLoad) { ret->allocate(); - else + } else if (!request.isCacheMaintenance()) { + // CMOs are treated as stores but they don't have data. All + // stores otherwise need to allocate for data. ret->dataDynamic(data); + } return ret; } |