summaryrefslogtreecommitdiff
path: root/src/cpu/minor/lsq.hh
diff options
context:
space:
mode:
authorMitch Hayenga <mitch.hayenga@arm.com>2016-07-21 17:19:16 +0100
committerMitch Hayenga <mitch.hayenga@arm.com>2016-07-21 17:19:16 +0100
commitff4009ac005be0347015f8ba5a8e37a3aa930e69 (patch)
treeb80cfa7c70c0e39f54c8c3d78527722cb6658510 /src/cpu/minor/lsq.hh
parent8a476d387c84f037d0ccf3cc20dc88870ab45fec (diff)
downloadgem5-ff4009ac005be0347015f8ba5a8e37a3aa930e69.tar.xz
cpu: Add SMT support to MinorCPU
This patch adds SMT support to the MinorCPU. Currently RoundRobin or Random thread scheduling are supported. Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
Diffstat (limited to 'src/cpu/minor/lsq.hh')
-rw-r--r--src/cpu/minor/lsq.hh8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index 09fb30d03..e0b72177c 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -537,7 +537,7 @@ class LSQ : public Named
/** Most recent execSeqNum of a memory barrier instruction or
* 0 if there are no in-flight barriers. Useful as a
* dependency for early-issued memory operations */
- InstSeqNum lastMemBarrier;
+ std::vector<InstSeqNum> lastMemBarrier;
public:
/** Retry state of last issued memory transfer */
@@ -640,6 +640,9 @@ class LSQ : public Named
/** Can a request be sent to the memory system */
bool canSendToMemorySystem();
+ /** Snoop other threads monitors on memory system accesses */
+ void threadSnoop(LSQRequestPtr request);
+
public:
LSQ(std::string name_, std::string dcache_port_name_,
MinorCPU &cpu_, Execute &execute_,
@@ -691,7 +694,8 @@ class LSQ : public Named
void issuedMemBarrierInst(MinorDynInstPtr inst);
/** Get the execSeqNum of the last issued memory barrier */
- InstSeqNum getLastMemBarrier() const { return lastMemBarrier; }
+ InstSeqNum getLastMemBarrier(ThreadID thread_id) const
+ { return lastMemBarrier[thread_id]; }
/** Is there nothing left in the LSQ */
bool isDrained();