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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-04 09:40:19 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
| commit | f54020eb8155371725ab75b0fc5c419287eca084 (patch) | |
| tree | 65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/cpu/minor/lsq.hh | |
| parent | 2113b21996d086dab32b9fd388efe3df241bfbd2 (diff) | |
| download | gem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz | |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/minor/lsq.hh')
| -rw-r--r-- | src/cpu/minor/lsq.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh index 9ee40f5d3..da873b4ac 100644 --- a/src/cpu/minor/lsq.hh +++ b/src/cpu/minor/lsq.hh @@ -143,7 +143,7 @@ class LSQ : public Named PacketPtr packet; /** The underlying request of this LSQRequest */ - Request request; + RequestPtr request; /** Fault generated performing this request */ Fault fault; @@ -272,7 +272,7 @@ class LSQ : public Named { protected: /** TLB interace */ - void finish(const Fault &fault_, RequestPtr request_, + void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseTLB::Mode mode) { } @@ -333,7 +333,7 @@ class LSQ : public Named { protected: /** TLB interace */ - void finish(const Fault &fault_, RequestPtr request_, + void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseTLB::Mode mode); /** Has my only packet been sent to the memory system but has not @@ -406,7 +406,7 @@ class LSQ : public Named protected: /** TLB response interface */ - void finish(const Fault &fault_, RequestPtr request_, + void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseTLB::Mode mode); public: @@ -720,7 +720,7 @@ class LSQ : public Named /** Make a suitable packet for the given request. If the request is a store, * data will be the payload data. If sender_state is NULL, it won't be * pushed into the packet as senderState */ -PacketPtr makePacketForRequest(Request &request, bool isLoad, +PacketPtr makePacketForRequest(const RequestPtr &request, bool isLoad, Packet::SenderState *sender_state = NULL, PacketDataPtr data = NULL); } |