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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
| commit | 608641e23c7f2288810c3f23a1a63790b664f2ab (patch) | |
| tree | 0656aaf9653e8d263f5daac0d5f0fe3190193ae5 /src/cpu/minor/scoreboard.cc | |
| parent | 6e354e82d9395b20f5f148cd545d0666b626e8ac (diff) | |
| download | gem5-608641e23c7f2288810c3f23a1a63790b664f2ab.tar.xz | |
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.
Diffstat (limited to 'src/cpu/minor/scoreboard.cc')
| -rw-r--r-- | src/cpu/minor/scoreboard.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc index f6b1f7944..3eb09271a 100644 --- a/src/cpu/minor/scoreboard.cc +++ b/src/cpu/minor/scoreboard.cc @@ -71,6 +71,11 @@ Scoreboard::findIndex(RegIndex reg, Index &scoreboard_index) scoreboard_index = TheISA::NumIntRegs + reg - TheISA::FP_Reg_Base; ret = true; break; + case VectorRegClass: + scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs + + TheISA::NumFloatRegs + reg - TheISA::Vector_Reg_Base; + ret = true; + break; case MiscRegClass: /* Don't bother with Misc registers */ ret = false; @@ -99,6 +104,9 @@ flattenRegIndex(TheISA::RegIndex reg, ThreadContext *thread_context) case CCRegClass: ret = thread_context->flattenCCIndex(reg); break; + case VectorRegClass: + ret = thread_context->flattenVectorIndex(reg); + break; case MiscRegClass: /* Don't bother to flatten misc regs as we don't need them here */ /* return thread_context->flattenMiscIndex(reg); */ |