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authorGabe Black <gabeblack@google.com>2018-11-19 17:20:31 -0800
committerGabe Black <gabeblack@google.com>2018-12-20 19:27:51 +0000
commit88bbabe93f339f9db301caf43bf2cca2a0e8048c (patch)
tree66323afaa9348f392deafe11d88973fd3034001b /src/cpu/minor
parent67d58e81825d7dff17def2cfeedf5d958141be55 (diff)
downloadgem5-88bbabe93f339f9db301caf43bf2cca2a0e8048c.tar.xz
arch, cpu: Remove float type accessors.
Use the binary accessors instead. Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2 Reviewed-on: https://gem5-review.googlesource.com/c/14457 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/minor')
-rw-r--r--src/cpu/minor/exec_context.hh19
1 files changed, 1 insertions, 18 deletions
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 238d11352..19bae74bf 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -99,7 +99,7 @@ class ExecContext : public ::ExecContext
setPredicate(true);
thread.setIntReg(TheISA::ZeroReg, 0);
#if THE_ISA == ALPHA_ISA
- thread.setFloatReg(TheISA::ZeroReg, 0.0);
+ thread.setFloatRegBits(TheISA::ZeroReg, 0);
#endif
}
@@ -129,14 +129,6 @@ class ExecContext : public ::ExecContext
return thread.readIntReg(reg.index());
}
- TheISA::FloatReg
- readFloatRegOperand(const StaticInst *si, int idx) override
- {
- const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isFloatReg());
- return thread.readFloatReg(reg.index());
- }
-
TheISA::FloatRegBits
readFloatRegOperandBits(const StaticInst *si, int idx) override
{
@@ -178,15 +170,6 @@ class ExecContext : public ::ExecContext
}
void
- setFloatRegOperand(const StaticInst *si, int idx,
- TheISA::FloatReg val) override
- {
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isFloatReg());
- thread.setFloatReg(reg.index(), val);
- }
-
- void
setFloatRegOperandBits(const StaticInst *si, int idx,
TheISA::FloatRegBits val) override
{