Revert power patch sets with unexpected interactions

The following patches had unexpected interactions with the current
upstream code and have been reverted for now:

e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

--HG--
extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508

3 files changed, 5 insertions, 9 deletions

diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index a707c6045..cd39a8b93 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -287,8 +287,6 @@ MinorCPU::activateContext(ThreadID thread_id)
     threads[thread_id]->activate();
     wakeupOnEvent(Minor::Pipeline::CPUStageId);
     pipeline->wakeupFetch();
-
-    BaseCPU::activateContext(thread_id);
 }
 
 void
@@ -297,8 +295,6 @@ MinorCPU::suspendContext(ThreadID thread_id)
     DPRINTF(MinorCPU, "SuspendContext %d\n", thread_id);
 
     threads[thread_id]->suspend();
-
-    BaseCPU::suspendContext(thread_id);
 }
 
 void
diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index d19d7b042..84aaf02f5 100644
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -135,7 +135,8 @@ Fetch1::fetchLine()
         "%s addr: 0x%x pc: %s line_offset: %d request_size: %d\n",
         request_id, aligned_pc, pc, line_offset, request_size);
 
-    request->request.setContext(cpu.threads[0]->getTC()->contextId());
+    request->request.setThreadContext(cpu.threads[0]->getTC()->contextId(),
+                                      /* thread id */ 0);
     request->request.setVirt(0 /* asid */,
         aligned_pc, request_size, Request::INST_FETCH, cpu.instMasterId(),
         /* I've no idea why we need the PC, but give it */
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index b5c0bc974..e0c5796c8 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -422,7 +422,7 @@ LSQ::SplitDataRequest::makeFragmentRequests()
 
         Request *fragment = new Request();
 
-        fragment->setContext(request.contextId());
+        fragment->setThreadContext(request.contextId(), /* thread id */ 0);
         fragment->setVirt(0 /* asid */,
             fragment_addr, fragment_size, request.getFlags(),
             request.masterId(),
@@ -1070,8 +1070,7 @@ LSQ::tryToSend(LSQRequestPtr request)
 
         if (request->request.isMmappedIpr()) {
             ThreadContext *thread =
-                cpu.getContext(cpu.contextToThread(
-                                request->request.contextId()));
+                cpu.getContext(request->request.threadId());
 
             if (request->isLoad) {
                 DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst));
@@ -1503,7 +1502,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
         inst->traceData->setMem(addr, size, flags);
 
     int cid = cpu.threads[inst->id.threadId]->getTC()->contextId();
-    request->request.setContext(cid);
+    request->request.setThreadContext(cid, /* thread id */ 0);
     request->request.setVirt(0 /* asid */,
         addr, size, flags, cpu.dataMasterId(),
         /* I've no idea why we need the PC, but give it */