arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

5 files changed, 86 insertions, 73 deletions

diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index 16af15bd7..42c370a70 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -133,15 +133,15 @@ operator <<(std::ostream &os, const MinorDynInst &inst)
 /** Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer,
  *  float, misc and zero registers given an 'architectural register number' */
 static void
-printRegName(std::ostream &os, TheISA::RegIndex reg)
+printRegName(std::ostream &os, RegId reg)
 {
-    RegClass reg_class = regIdxToClass(reg);
+    RegClass reg_class = reg.regClass;
 
     switch (reg_class)
     {
       case MiscRegClass:
         {
-            TheISA::RegIndex misc_reg = reg - TheISA::Misc_Reg_Base;
+            RegIndex misc_reg = reg.regIdx;
 
         /* This is an ugly test because not all archs. have miscRegName */
 #if THE_ISA == ARM_ISA
@@ -153,17 +153,17 @@ printRegName(std::ostream &os, TheISA::RegIndex reg)
         }
         break;
       case FloatRegClass:
-        os << 'f' << static_cast<unsigned int>(reg - TheISA::FP_Reg_Base);
+        os << 'f' << static_cast<unsigned int>(reg.regIdx);
         break;
       case IntRegClass:
-        if (reg == TheISA::ZeroReg) {
+        if (reg.isZeroReg()) {
             os << 'z';
         } else {
-            os << 'r' << static_cast<unsigned int>(reg);
+            os << 'r' << static_cast<unsigned int>(reg.regIdx);
         }
         break;
       case CCRegClass:
-        os << 'c' << static_cast<unsigned int>(reg - TheISA::CC_Reg_Base);
+        os << 'c' << static_cast<unsigned int>(reg.regIdx);
     }
 }
 
diff --git a/src/cpu/minor/dyn_inst.hh b/src/cpu/minor/dyn_inst.hh
index a30d68819..79c9ca4a4 100644
--- a/src/cpu/minor/dyn_inst.hh
+++ b/src/cpu/minor/dyn_inst.hh
@@ -219,7 +219,7 @@ class MinorDynInst : public RefCounted
     /** Flat register indices so that, when clearing the scoreboard, we
      *  have the same register indices as when the instruction was marked
      *  up */
-    TheISA::RegIndex flatDestRegIdx[TheISA::MaxInstDestRegs];
+    RegId flatDestRegIdx[TheISA::MaxInstDestRegs];
 
     /** Effective address as set by ExecContext::setEA */
     Addr ea;
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 6b2eae0f1..d517d5abb 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -124,43 +124,51 @@ class ExecContext : public ::ExecContext
     IntReg
     readIntRegOperand(const StaticInst *si, int idx) override
     {
-        return thread.readIntReg(si->srcRegIdx(idx));
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == IntRegClass);
+        return thread.readIntReg(reg.regIdx);
     }
 
     TheISA::FloatReg
     readFloatRegOperand(const StaticInst *si, int idx) override
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
-        return thread.readFloatReg(reg_idx);
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == FloatRegClass);
+        return thread.readFloatReg(reg.regIdx);
     }
 
     TheISA::FloatRegBits
     readFloatRegOperandBits(const StaticInst *si, int idx) override
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
-        return thread.readFloatRegBits(reg_idx);
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == FloatRegClass);
+        return thread.readFloatRegBits(reg.regIdx);
     }
 
     void
     setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
     {
-        thread.setIntReg(si->destRegIdx(idx), val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == IntRegClass);
+        thread.setIntReg(reg.regIdx, val);
     }
 
     void
     setFloatRegOperand(const StaticInst *si, int idx,
         TheISA::FloatReg val) override
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
-        thread.setFloatReg(reg_idx, val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == FloatRegClass);
+        thread.setFloatReg(reg.regIdx, val);
     }
 
     void
     setFloatRegOperandBits(const StaticInst *si, int idx,
         TheISA::FloatRegBits val) override
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
-        thread.setFloatRegBits(reg_idx, val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == FloatRegClass);
+        thread.setFloatRegBits(reg.regIdx, val);
     }
 
     bool
@@ -208,16 +216,18 @@ class ExecContext : public ::ExecContext
     TheISA::MiscReg
     readMiscRegOperand(const StaticInst *si, int idx) override
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
-        return thread.readMiscReg(reg_idx);
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == MiscRegClass);
+        return thread.readMiscReg(reg.regIdx);
     }
 
     void
     setMiscRegOperand(const StaticInst *si, int idx,
         const TheISA::MiscReg &val) override
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
-        return thread.setMiscReg(reg_idx, val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == MiscRegClass);
+        return thread.setMiscReg(reg.regIdx, val);
     }
 
     Fault
@@ -269,15 +279,17 @@ class ExecContext : public ::ExecContext
     TheISA::CCReg
     readCCRegOperand(const StaticInst *si, int idx) override
     {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
-        return thread.readCCReg(reg_idx);
+        RegId reg = si->srcRegIdx(idx);
+        assert(reg.regClass == CCRegClass);
+        return thread.readCCReg(reg.regIdx);
     }
 
     void
     setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
     {
-        int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
-        thread.setCCReg(reg_idx, val);
+        RegId reg = si->destRegIdx(idx);
+        assert(reg.regClass == CCRegClass);
+        thread.setCCReg(reg.regIdx, val);
     }
 
     void
@@ -308,37 +320,46 @@ class ExecContext : public ::ExecContext
 
     /* MIPS: other thread register reading/writing */
     uint64_t
-    readRegOtherThread(int idx, ThreadID tid = InvalidThreadID)
+    readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID)
     {
         SimpleThread *other_thread = (tid == InvalidThreadID
             ? &thread : cpu.threads[tid]);
 
-        if (idx < TheISA::FP_Reg_Base) { /* Integer */
-            return other_thread->readIntReg(idx);
-        } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
-            return other_thread->readFloatRegBits(idx
-                - TheISA::FP_Reg_Base);
-        } else { /* Misc */
-            return other_thread->readMiscReg(idx
-                - TheISA::Misc_Reg_Base);
+        switch(reg.regClass) {
+            case IntRegClass:
+                return other_thread->readIntReg(reg.regIdx);
+                break;
+            case FloatRegClass:
+                return other_thread->readFloatRegBits(reg.regIdx);
+                break;
+            case MiscRegClass:
+                return other_thread->readMiscReg(reg.regIdx);
+            default:
+                panic("Unexpected reg class! (%s)",
+                      RegClassStrings[reg.regClass]);
+                return 0;
         }
     }
 
     void
-    setRegOtherThread(int idx, const TheISA::MiscReg &val,
+    setRegOtherThread(RegId reg, const TheISA::MiscReg &val,
         ThreadID tid = InvalidThreadID)
     {
         SimpleThread *other_thread = (tid == InvalidThreadID
             ? &thread : cpu.threads[tid]);
 
-        if (idx < TheISA::FP_Reg_Base) { /* Integer */
-            return other_thread->setIntReg(idx, val);
-        } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
-            return other_thread->setFloatRegBits(idx
-                - TheISA::FP_Reg_Base, val);
-        } else { /* Misc */
-            return other_thread->setMiscReg(idx
-                - TheISA::Misc_Reg_Base, val);
+         switch(reg.regClass) {
+            case IntRegClass:
+                return other_thread->setIntReg(reg.regIdx, val);
+                break;
+            case FloatRegClass:
+                return other_thread->setFloatRegBits(reg.regIdx, val);
+                break;
+            case MiscRegClass:
+                return other_thread->setMiscReg(reg.regIdx, val);
+            default:
+                panic("Unexpected reg class! (%s)",
+                      RegClassStrings[reg.regClass]);
         }
     }
 
diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index 4de3f9522..31657b310 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -48,28 +48,27 @@ namespace Minor
 {
 
 bool
-Scoreboard::findIndex(RegIndex reg, Index &scoreboard_index)
+Scoreboard::findIndex(RegId reg, Index &scoreboard_index)
 {
-    RegClass reg_class = regIdxToClass(reg);
     bool ret = false;
 
-    if (reg == TheISA::ZeroReg) {
+    if (reg.isZeroReg()) {
         /* Don't bother with the zero register */
         ret = false;
     } else {
-        switch (reg_class)
+        switch (reg.regClass)
         {
           case IntRegClass:
-            scoreboard_index = reg;
+            scoreboard_index = reg.regIdx;
             ret = true;
             break;
           case FloatRegClass:
             scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
-                reg - TheISA::FP_Reg_Base;
+                reg.regIdx;
             ret = true;
             break;
           case CCRegClass:
-            scoreboard_index = TheISA::NumIntRegs + reg - TheISA::FP_Reg_Base;
+            scoreboard_index = TheISA::NumIntRegs + reg.regIdx;
             ret = true;
             break;
           case MiscRegClass:
@@ -82,32 +81,28 @@ Scoreboard::findIndex(RegIndex reg, Index &scoreboard_index)
     return ret;
 }
 
-/** Flatten a RegIndex, irrespective of what reg type it's pointing to */
-static TheISA::RegIndex
-flattenRegIndex(TheISA::RegIndex reg, ThreadContext *thread_context)
+/** Flatten a RegId, irrespective of what reg type it's pointing to */
+static RegId
+flattenRegIndex(RegId reg, ThreadContext *thread_context)
 {
-    RegClass reg_class = regIdxToClass(reg);
-    TheISA::RegIndex ret = reg;
-
-    switch (reg_class)
+    switch (reg.regClass)
     {
       case IntRegClass:
-        ret = thread_context->flattenIntIndex(reg);
+        reg.regIdx = thread_context->flattenIntIndex(reg.regIdx);
         break;
       case FloatRegClass:
-        ret = thread_context->flattenFloatIndex(reg);
+        reg.regIdx = thread_context->flattenFloatIndex(reg.regIdx);
         break;
       case CCRegClass:
-        ret = thread_context->flattenCCIndex(reg);
+        reg.regIdx = thread_context->flattenCCIndex(reg.regIdx);
         break;
       case MiscRegClass:
         /* Don't bother to flatten misc regs as we don't need them here */
         /* return thread_context->flattenMiscIndex(reg); */
-        ret = reg;
         break;
     }
 
-    return ret;
+    return reg;
 }
 
 void
@@ -124,8 +119,8 @@ Scoreboard::markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
     for (unsigned int dest_index = 0; dest_index < num_dests;
         dest_index++)
     {
-        RegIndex reg = flattenRegIndex(
-            staticInst->destRegIdx(dest_index), thread_context);
+        RegId reg = flattenRegIndex(
+                staticInst->destRegIdx(dest_index), thread_context);
         Index index;
 
         if (findIndex(reg, index)) {
@@ -148,7 +143,7 @@ Scoreboard::markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
                 *inst, index, numResults[index], returnCycle[index]);
         } else {
             /* Use ZeroReg to mark invalid/untracked dests */
-            inst->flatDestRegIdx[dest_index] = TheISA::ZeroReg;
+            inst->flatDestRegIdx[dest_index] = RegId::zeroReg;
         }
     }
 }
@@ -166,7 +161,7 @@ Scoreboard::execSeqNumToWaitFor(MinorDynInstPtr inst,
     unsigned int num_srcs = staticInst->numSrcRegs();
 
     for (unsigned int src_index = 0; src_index < num_srcs; src_index++) {
-        RegIndex reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
+        RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
             thread_context);
         unsigned short int index;
 
@@ -195,7 +190,7 @@ Scoreboard::clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable)
     for (unsigned int dest_index = 0; dest_index < num_dests;
         dest_index++)
     {
-        RegIndex reg = inst->flatDestRegIdx[dest_index];
+        RegId reg = inst->flatDestRegIdx[dest_index];
         Index index;
 
         if (findIndex(reg, index)) {
@@ -252,7 +247,7 @@ Scoreboard::canInstIssue(MinorDynInstPtr inst,
     while (src_index < num_srcs && /* More registers */
         ret /* Still possible */)
     {
-        RegIndex reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
+        RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
             thread_context);
         unsigned short int index;
 
diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh
index 711bcafb2..815d81408 100644
--- a/src/cpu/minor/scoreboard.hh
+++ b/src/cpu/minor/scoreboard.hh
@@ -67,9 +67,6 @@ class Scoreboard : public Named
      *  [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */
     const unsigned numRegs;
 
-    /** Type to use for thread context registers */
-    typedef TheISA::RegIndex RegIndex;
-
     /** Type to use when indexing numResults */
     typedef unsigned short int Index;
 
@@ -109,7 +106,7 @@ class Scoreboard : public Named
     /** Sets scoreboard_index to the index into numResults of the
      *  given register index.  Returns true if the given register
      *  is in the scoreboard and false if it isn't */
-    bool findIndex(RegIndex reg, Index &scoreboard_index);
+    bool findIndex(RegId reg, Index &scoreboard_index);
 
     /** Mark up an instruction's effects by incrementing
      *  numResults counts.  If mark_unpredictable is true, the inst's