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authorMitch Hayenga <mitch.hayenga@arm.com>2016-04-05 12:39:21 -0500
committerMitch Hayenga <mitch.hayenga@arm.com>2016-04-05 12:39:21 -0500
commit8615b27174ae06db4665016c877b1e88031af203 (patch)
tree7b28888f71e7e41e84d4087b6ccb53670e04582b /src/cpu/minor
parent76ee011a12ade238d5cbf4b570e1d34d7ba72687 (diff)
downloadgem5-8615b27174ae06db4665016c877b1e88031af203.tar.xz
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu.
Diffstat (limited to 'src/cpu/minor')
-rw-r--r--src/cpu/minor/fetch1.cc3
-rw-r--r--src/cpu/minor/lsq.cc7
2 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index 84aaf02f5..d19d7b042 100644
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -135,8 +135,7 @@ Fetch1::fetchLine()
"%s addr: 0x%x pc: %s line_offset: %d request_size: %d\n",
request_id, aligned_pc, pc, line_offset, request_size);
- request->request.setThreadContext(cpu.threads[0]->getTC()->contextId(),
- /* thread id */ 0);
+ request->request.setContext(cpu.threads[0]->getTC()->contextId());
request->request.setVirt(0 /* asid */,
aligned_pc, request_size, Request::INST_FETCH, cpu.instMasterId(),
/* I've no idea why we need the PC, but give it */
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index e0c5796c8..b5c0bc974 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -422,7 +422,7 @@ LSQ::SplitDataRequest::makeFragmentRequests()
Request *fragment = new Request();
- fragment->setThreadContext(request.contextId(), /* thread id */ 0);
+ fragment->setContext(request.contextId());
fragment->setVirt(0 /* asid */,
fragment_addr, fragment_size, request.getFlags(),
request.masterId(),
@@ -1070,7 +1070,8 @@ LSQ::tryToSend(LSQRequestPtr request)
if (request->request.isMmappedIpr()) {
ThreadContext *thread =
- cpu.getContext(request->request.threadId());
+ cpu.getContext(cpu.contextToThread(
+ request->request.contextId()));
if (request->isLoad) {
DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst));
@@ -1502,7 +1503,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
inst->traceData->setMem(addr, size, flags);
int cid = cpu.threads[inst->id.threadId]->getTC()->contextId();
- request->request.setThreadContext(cid, /* thread id */ 0);
+ request->request.setContext(cid);
request->request.setVirt(0 /* asid */,
addr, size, flags, cpu.dataMasterId(),
/* I've no idea why we need the PC, but give it */