arch: Pass faults by const reference where possible

This patch changes how faults are passed between methods in an attempt
to copy as few reference-counting pointer instances as possible. This
should avoid unecessary copies being created, contributing to the
increment/decrement of the reference counters.

4 files changed, 14 insertions, 14 deletions

diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index 45dc5eddc..79a5d0a78 100644
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -204,8 +204,8 @@ Fetch1::FetchRequest::makePacket()
 }
 
 void
-Fetch1::FetchRequest::finish(
-    Fault fault_, RequestPtr request_, ThreadContext *tc, BaseTLB::Mode mode)
+Fetch1::FetchRequest::finish(const Fault &fault_, RequestPtr request_,
+                             ThreadContext *tc, BaseTLB::Mode mode)
 {
     fault = fault_;
 
diff --git a/src/cpu/minor/fetch1.hh b/src/cpu/minor/fetch1.hh
index 29a63d1f1..45977b310 100644
--- a/src/cpu/minor/fetch1.hh
+++ b/src/cpu/minor/fetch1.hh
@@ -163,8 +163,8 @@ class Fetch1 : public Named
         /** Interface for ITLB responses.  Populates self and then passes
          *  the request on to the ports' handleTLBResponse member
          *  function */
-        void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
-            BaseTLB::Mode mode);
+        void finish(const Fault &fault_, RequestPtr request_,
+                    ThreadContext *tc, BaseTLB::Mode mode);
 
       public:
         FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index b05ae514c..0a473af89 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -226,8 +226,8 @@ LSQ::clearMemBarrier(MinorDynInstPtr inst)
 }
 
 void
-LSQ::SingleDataRequest::finish(Fault fault_, RequestPtr request_,
-    ThreadContext *tc, BaseTLB::Mode mode)
+LSQ::SingleDataRequest::finish(const Fault &fault_, RequestPtr request_,
+                               ThreadContext *tc, BaseTLB::Mode mode)
 {
     fault = fault_;
 
@@ -273,8 +273,8 @@ LSQ::SingleDataRequest::retireResponse(PacketPtr packet_)
 }
 
 void
-LSQ::SplitDataRequest::finish(Fault fault_, RequestPtr request_,
-    ThreadContext *tc, BaseTLB::Mode mode)
+LSQ::SplitDataRequest::finish(const Fault &fault_, RequestPtr request_,
+                              ThreadContext *tc, BaseTLB::Mode mode)
 {
     fault = fault_;
 
diff --git a/src/cpu/minor/lsq.hh b/src/cpu/minor/lsq.hh
index 183986826..7da2fd694 100644
--- a/src/cpu/minor/lsq.hh
+++ b/src/cpu/minor/lsq.hh
@@ -268,8 +268,8 @@ class LSQ : public Named
     {
       protected:
         /** TLB interace */
-        void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
-            BaseTLB::Mode mode)
+        void finish(const Fault &fault_, RequestPtr request_,
+                    ThreadContext *tc, BaseTLB::Mode mode)
         { }
 
       public:
@@ -329,8 +329,8 @@ class LSQ : public Named
     {
       protected:
         /** TLB interace */
-        void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
-            BaseTLB::Mode mode);
+        void finish(const Fault &fault_, RequestPtr request_,
+                    ThreadContext *tc, BaseTLB::Mode mode);
 
         /** Has my only packet been sent to the memory system but has not
          *  yet been responded to */
@@ -415,8 +415,8 @@ class LSQ : public Named
 
       protected:
         /** TLB response interface */
-        void finish(Fault fault_, RequestPtr request_, ThreadContext *tc,
-            BaseTLB::Mode mode);
+        void finish(const Fault &fault_, RequestPtr request_,
+                    ThreadContext *tc, BaseTLB::Mode mode);
 
       public:
         SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,